LTC4212CMS datasheet(12/24 Pages) LINER

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LTC4212

4212f

Since the PGT is pulled to GND by M12 before the power

good circuit is enabled, the first positive ramp at the PGT

pin starts from 0V instead of the 0.65V for the subsequent

13 cycles.

Power Good Time-Out

At the end of the time-out period, the PGI pin is sampled.

M12 is turned on to discharge CPGT to ground. If the PGI

pin is low when sampled, the DC/DC converters have not

entered into regulation on time and the power good circuit

trips the circuit breaker to latch off the board. If PGI is high

when sampled, the converters powered up into regulation

on time and the board is left powered up. The power good

glitch filter is enabled and it monitors the PGI pin for a low,

an indication that at least one DC/DC converter has dropped

out of regulation. The glitch filter rejects low pulses

shorter than a programmable period.

Power Good Glitch Filter

A glitch filter consisting of COMP5, M5 and a 5

µA current

source rejects PGI low pulses that are shorter than the

duration programmed by an external capacitor, CPGF,

connected from the PGF pin to GND.

Once the glitch filter is enabled, M5 is switched off

whenever PGI goes low. This allows an internal 5

µA

current source to charge the capacitor at the PGF pin. If

PGI stays low for long enough, the voltage at the PGF pin

rises above the upper threshold of COMP5 (1.236V) and

causes the power good circuit to trip the circuit breaker.

For a given CPGF capacitance connected between PGF and

GND, the minimum low PGI pulse width needed to trip the

circuit breaker is given by:

tPGF = 1.236V • (CPGF)/5µA + 5µs

(4)

An internal 5pF capacitor and stray MSOP-10 package

capacitance sets tPGF to 5µs nominal when CPGF is omit-

ted. Table 3 shows tPGF values for various standard

capacitors. Tying the PGF pin to ground prevents the

power good glitch filter from tripping the circuit breaker

after normal power-up.

OPERATIO

Table 3. tPGF vs CPGF

CPGF

tPGF

—5

µs

10pF

7.5

µs

22pF

10.4

µs

33pF

13.2

µs

47pF

16.6

µs

68pF

21.8

µs

82pF

25.2

µs

100pF

29.7

µs

220pF

59.3

µs

330pF

86.6

µs

470pF

121.2

µs

680pF

173

µs

820pF

208

µs

1nF

252

µs

Soft-Start or Inrush Current Control

The LTC4212 monitors the load current by sensing the

voltage (VCC – VSENSE) developed across an external

sense resistor (RSENSE) connected between the VCC and

SENSE pins. During the second timing cycle (see Normal

Operating Sequence) a soft-start circuit turns on the

external N-channel FET gradually to keep inrush currents

in check. The soft-start circuit monitors and servos the

voltage across RSENSE to 50mV by either connecting a

µA pull-up current source to the GATE pin when the

voltage across RSENSE is less than 50mV or discharging it

with a 10

µA pull-down current source when the voltage

rises above 50mV. Therefore, the inrush current from the

backplane supply is limited to:

ILIMIT(SOFTSTART) = 50mV/RSENSE

(5)

For example, ILIMIT(SOFTSTART) = 5A when RSENSE = 0.01Ω.

Assuming that the voltage across the sense resistor does

not exceed 50mV, the voltage at the GATE pin rises at rate

given by:

VGATE Slew Rate = dVGATE/dt =10µA/CGATE

(6)

where, CGATE = Power MOSFET gate input capacitance

(CISS).

For example, an Si4410DY (a 30V N-channel power

MOSFET) exhibits an approximate CGATE of 3300pF at

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