ADF4154BCP datasheet(16/20 Pages) AD

16 / 20 page

ADF4154

Rev. 0 | Page 16 of 20

RF Charge Pump Three-State

This bit puts the charge pump into three-state mode when

programmed to 1. It should be set to 0 for normal operation.

RF Power-Down

DB4 on the ADF4154 provides the programmable power-down

mode. Setting Bit DB4 to 1 powers down the device. Setting

Bit DB4 to 0 returns the synthesizer to normal operation. While

in software power-down mode, the part retains all information

in its registers. Only when supplies are removed are the register

contents lost.

When a power-down is activated, the following events occur:

All active dc current paths are removed.

The synthesizer counters are forced to their load

state conditions.

The charge pump is forced into three-state mode.

The digital lock detect circuitry is reset.

The RFIN input is de-biased.

The input register remains active and capable of loading

and latching data.

Lock Detect Precision (LDP)

When the LDP bit is programmed to 0, 24 consecutive reference

cycles of 15 ns must occur before the digital lock detect is set.

When this bit is programmed to 1, 40 consecutive reference

cycles of 15 ns must occur before digital lock detect is set.

Phase Detector Polarity

DB6 in the ADF4154 sets the phase detector polarity. When the

VCO characteristics are positive, this should be set to 1. When

they are negative, it should be set to 0.

Charge Pump Current Setting

DB7, DB8, DB9, and DB10 set the charge pump current, which

should be set according to the loop filter design (see Table 10).

REFIN Doubler

Setting the REFIN bit to 0 feeds the REFIN signal directly to the

4-bit RF R counter, which disables the doubler. Setting the REFIN

bit to 1 multiplies the REFIN frequency by a factor of 2 before

feeding into the 4-bit R counter. When the doubler is disabled,

the REFIN falling edge is the active edge at the PFD input to the

fractional synthesizer. When the doubler is enabled, both the

rising and falling edges of REFIN become active edges at the

PFD input.

When the doubler is enabled and the lowest spur mode is

chosen, the in-band phase noise performance is sensitive to the

REFIN duty cycle. The phase noise degradation can be as much

as 5 dB for the REFIN duty cycles outside a 45% to 55% range.

The phase noise is insensitive to the REFIN duty cycle in the

lowest noise mode and in the lowest noise and spur mode. The

phase noise is insensitive to the REFIN duty cycle when the

doubler is disabled.

NOISE AND SPUR REGISTER, R3

The on-chip noise and spur register is programmed by setting

R3[1, 0] to [1, 1]. Table 7 shows the input data format for

programming this register.

Noise and Spur Mode

Noise and spur mode allows the user to optimize a design either

for improved spurious performance or for improved phase

noise performance. When the lowest spur setting is chosen,

dither is enabled. This randomizes the fractional quantization

noise so that it looks more like white noise rather than spurious

noise. This means that the part is optimized for improved

spurious performance. This operation would normally be used

when the PLL closed-loop bandwidth is wide for fast-locking

applications. A wide-loop bandwidth is seen as a loop

bandwidth greater than 1/10 of the RFOUT channel step

resolution (fRES). A wide-loop filter does not attenuate the spurs

to a level that a narrow-loop bandwidth would. When the low

noise and spur setting is enabled, dither is disabled. This

optimizes the synthesizer to operate with improved noise

performance. However, the spurious performance is degraded

in this mode compared to the lowest spurs setting. To further

improve noise performance, the lowest noise setting option can

be used, which reduces the phase noise. As well as disabling the

dither, it ensures that the charge pump operates in an optimum

region for noise performance. This setting is extremely useful

where a narrow-loop filter bandwidth is available. The

synthesizer ensures extremely low noise and the filter attenuates

the spurs. The typical performance characteristics give the user

an idea of the trade-off in a typical WCDMA setup for the

different noise and spur settings.

RESERVED BITS

These bits should be set to 0 for normal operation.

RF SYNTHESIZER: A WORKED EXAMPLE

This equation governs how the synthesizer should be

programmed.

RFOUT

= [INT + (FRAC/MOD)] × [FPFD]

(3)

where:

RFOUT

is the RF frequency output.

INT

is the integer division factor.

FRAC

is the fractionality.

MOD

is the modulus.

FPFD

= [REFIN × (1 = D)/R]

(4)

where:

REFIN

is the reference frequency input.

is the RF REFIN doubler bit.

is the RF reference division factor.

ADF4154BCP датащи(PDF) 16 Page - Analog Devices

ADF4154BCP датащи(HTML) 16 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

датащи скачать

ссылки URL