ADF4154BCP datasheet(6/20 Pages) AD

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ADF4154

Rev. 0 | Page 6 of 20

PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS

ADF4154

TOP VIEW

(Not to Scale)

AGND

RFINB 5

RFINA 6

AVDD 7

REFIN 8

DATA

CLK

SDVDD

DGND

RSET 1

CPGND

DVDD

MUXOUT

Figure 3. TSSOP Pin Configuration

MUXOUT

DATA

CLK

SDVDD

RFINA

RFINB

AGND

CPGND

ADF4154

TOP VIEW

PIN 1

INDICATOR

Figure 4. LFCSP Pin Configuration

Table 4. Pin Function Descriptions

TSSOP

LFCSP

Mnemonic

Description

RSET

Connecting a resistor between this pin and ground sets the maximum charge pump output current.

The relationship between ICP and RSET is

SET

max =

where RSET = 5.1 kΩ and ICPmax = 5 mA.

Charge Pump Output. When enabled, this provides ±ICP to the external loop filter, which in turn drives

the external VCO.

CPGND

Charge Pump Ground. This is the ground return path for the charge pump.

2, 3

AGND

Analog Ground. This is the ground return path of the prescaler.

RFINB

Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a

small bypass capacitor, typically 100 pF (see Figure 18).

RFINA

Input to the RF Prescaler. This small-signal input is normally ac-coupled from the VCO.

6, 7

AVDD

Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane should be

placed as close as possible to this pin. AVDD has a value of 3 V ± 10%. AVDD must have the same voltage

as DVDD.

REFIN

Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input

resistance of 100 kΩ (see Figure 17). This input can be driven from a TTL or CMOS crystal oscillator, or it

can be ac-coupled.

9, 10

DGND

Digital Ground.

SDVDD

Σ-∆ Power. Decoupling capacitors to the digital ground plane should be placed as close as possible to

this pin. SDVDD has a value of 3 V ± 10%. SDVDD must have the same voltage as DVDD.

CLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched

into the shift register on the CLK rising edge. This input is a high impedance CMOS input.

DATA

Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This input is a

high impedance CMOS input.

Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one of

the four latches, the latch being selected using the control bits.

MUXOUT

This multiplexer output allows either the RF lock detect, the scaled RF, or the scaled reference

frequency to be accessed externally.

16, 17

DVDD

Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground plane should

be placed as close as possible to this pin. DVDD has a value of 3 V ± 10%. DVDD must have the same

voltage as AVDD.

Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, it

can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.

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