5228-DS04-R datasheet(62/100 Pages) BOARDCOM

62 / 100 page

BCM5228

Data Sheet

7/12/04

Broa d c om Co rp o r a t i o n

Page 50

100BASE-X Receive Error Counter

Document

5228-DS09-405-R

R/SMII Overrun/Underrun Detected. The PHY returns a 1 in bit 11, when the RMII receive FIFO encounters an overrun

or underrun condition.

FX Mode. Returns a value derived from the SD± input pins. Returns a 1 when SD± are driven with a valid differential

signal level. Returns a 0 when both SD+ and SD– are simultaneously driven low.

Locked. The PHY returns a 1 in bit 9 when the descrambler is locked to the incoming data stream. Otherwise, it returns a 0.

Current 100BASE-X Link Status. The PHY returns a 1 in bit 8 when the 100BASE-X link status is good. Otherwise, it

returns a 0.

Remote Fault. The PHY returns a 1 while its link partner is signalling a far-end fault condition. Otherwise, it returns a 0.

False Carrier Detected. The PHY returns a 1 in bit 5 of the Extended Status register if a false carrier has been detected

since the last time this register was read. Otherwise, it returns a 0.

Bad ESD Detected. The PHY returns a 1 in bit 4 if an end-of-stream delimiter error has been detected since the last time

this register was read. Otherwise, it returns a 0.

Receive Error Detected. The PHY returns a 1 in bit 3 if a packet was received with an invalid code since the last time this

Transmit Error Detected. The PHY returns a 1 in bit 2 if a packet was received with a Transmit Error code since the last

time this register was read. Otherwise, it returns a 0.

Lock Error Detected. The PHY returns a 1 in bit 1 if the descrambler has lost lock since the last time this register was read.

Otherwise, it returns a 0.

MLT3 Code Error Detected. The PHY returns a 1 in bit 0 if an MLT3 coding error has been detected in the receive data

stream since the last time this register was read. Otherwise it returns a 0.

100BASE-X RECEIVE ERROR COUNTER

Receive Error Counter [15:0]. This counter increments each time the BCM5228 receives a non-collision packet containing

at least one receive error. The counter automatically clears itself when read. When the counter reaches its maximum value,

FFh, it stops counting receive errors until cleared

Table 29: 100BASE-X Receive Error Counter (Address 18d, 12h)

Bit

Name

R/W

Description

Default

15:0

Receive Error Counter [15:0]

R/W

Number of non-collision packets with receive errors

since last read

0000h

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