LM2648 datasheet(17/23 Pages) NSC

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Operation Descriptions (Continued)

Channel 3 Dual Phase Operation

Channel 3 consists of two 180˚ out of phase converters

operating in parallel to provide a single output voltage. In

high current demand applications, current sharing between

the two switching channels greatly reduces the stress and

heat on the output stage components while lowering input

ripple current. The sum of inductor ripple currents is also

reduced which results in lowered output ripple voltage.

When designing channel 3, simply design each switcher (3a

and 3b) to supply half of the load current. Accurate current

sensing is critical to ensure equal current sharing.

Since each switcher has separate current sense and limit

pins, channel 3 can also be operated in single phase mode.

This requires that either channel 3a or 3b remains unused.

To operate channel 3 as a single phase controller, make the

following pin connections to the unused channel. Connect

ILIM3x and KS3x to VIN, RSNS3x and SW3x to GND, leave

HDRV3x and LDRV3x open, and connect CBOOT3X to

VDD3X.

SWITCHING NOISE REDUCTION

Power MOSFETs are very fast switching devices. In syn-

chronous rectifier converters, the rapid increase of drain

current in the top FET coupled with parasitic inductance will

generate unwanted Ldi/dt noise spikes at the source node of

the FET (SWx node) and also at the VIN node. The magni-

tude of this noise will increase as the output current in-

creases. This parasitic spike noise may turn into electromag-

netic interference (EMI), and can also cause problems in

device performance. Therefore, it must be suppressed using

one of the following methods.

It is strongly recommended to add R-C filters to the current

sense amplifier inputs of channel 3 as shown in Figure 2.

This will reduce the susceptibility to switching noise, espe-

cially during heavy load transients and short on-time condi-

tions. The filter components should be connected as close

as possible to the IC.

As shown in Figure 3, adding a resistor in series with the

SWx pin will slow down the gate drive (HDRVx), thus slowing

the rise and fall time of the top FET, yielding a longer drain

current transition time.

Usually a 3.3

Ω to 4.7Ω resistor is sufficient to suppress the

noise. Top FET switching losses will increase with higher

resistance values.

Small resistors (1-5 ohms) can also be placed in series with

the HDRVx pin or the CBOOTx pin to effectively reduce

switch node ringing. A CBOOT resistor will slow the rise time

of the FET, whereas a resistor at HDRV will reduce both rise

and fall times.

OUTPUT VOLTAGE SETTING

The output voltage for each channel is set by the ratio of a

voltage divider as shown in Figure 4. The resistor values can

be determined by the following equation:

Although increasing the value of R1 and R2 will increase

efficiency, this will also decrease accuracy. In the case of

channels 1 and 2, increasing R2 will decrease loop gain,

resulting in degraded transient response. The output voltage

is limited by both maximum duty cycle and minimum on time.

It is recommended that the nominal output voltage does not

exceed 1V less than the minimum input voltage. In general,

the minimum possible output voltage is approximately 1.3V.

However, at maximum input voltage the minimum output will

be determined by the minimum on time (166ns typ.) and may

be as high as 1.35V for an input voltage of 18V.

For input voltages below 5.5V, VLIN5 should be connected

to VIN through a small resistor (approximately 4.7

Ω). This

will ensure that VLIN5 does not fall below the UVLO thresh-

old.

LAYOUT RECOMMENDATIONS

To ensure proper operation, a few key layout guidelines

should be followed.

The PGND and SGND pins and nodes should be connected

to isolated ground planes which connect at a single point.

This will help to keep the signal ground and thus the COMP

and FB pins isolated from switching noise.

All current sensing and limiting pins should be Kelvin con-

nected directly to the current sense points. This will help

ensure accurate current sensing and limiting.

All FB voltage dividers should be placed close to the device,

and the FB traces should be kept away from sources of

noise.

Input capacitors should be connected as close as possible to

the top of the current sense resistors.

Component Selection

INPUT CAPACITOR SELECTION

The fact that the switching channels of the LM2648 are 180˚

out of phase will reduce the RMS value of the ripple current

seen by the input capacitors. This will help extend input

capacitor life span and result in a more efficient system.

Input capacitors must be selected that can handle both the

maximum ripple RMS current at highest ambient tempera-

20059609

FIGURE 3. SW Series Resistor

20059611

FIGURE 4. Output Voltage Setting

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