FDMF5821 datasheet(15/26 Pages) ONSEMI

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FDMF5821 • Rev. 1.0

Low-Side MOSFET Off to High-Side MOSFET On

Dead Time in CCM1 / DCM

To prevent overlap during the low-side MOSFET off to

high-side MOSFET on switching transition, adaptive

circuitry monitors the voltage at the GL pin. When the

PWM signal goes HIGH, GL goes LOW after a

propagation delay (tPD_PHGLL). Once the GL pin is

discharged below ~ 1

– 2 V, GH is pulled HIGH after an

adaptive delay, tD_DEADON.

Some situations where the ZCD# rising-edge signal

leads the PWM rising edge by tens of nanoseconds,

can cause GH and GL overlap. This event can occur

when the PWM controller sends PWM and ZCD#

signals that lead, lag, or are synchronized. To avoid this

phenomenon, a secondary fixed propagation delay

(tFD_ON1) is added to ensure there is always a minimum

delay between low-side MOSFET off to high-side

MOSFET on.

Low-Side MOSFET Off to High-Side MOSFET On

Dead Time in CCM2

As noted in the CCM2 Operation section, the low-side

driver strength is scale-able upon detection of CCM2.

CCM2 feature slows the charge and discharge of the

low-side MOSFET gate to minimize peak switching

voltage overshoots during low-side MOSFET hard-

switching (negative inductor current). To avoid cross-

conduction, the slowing of the low-side gate also

requires an adjustment (increase) of the dead time

between low-side MOSFET off to high-side MOSFET

on.

fairly

long

fixed

dead

time

(tFD_ON2)

implemented to ensure there is no cross conduction

during this CCM2 operation.

High-Side MOSFET Off to Low-Side MOSFET On

Dead Time in CCM1 / DCM

To get very short dead time during high-side MOSFET

off to low-side MOSFET on transition, a fixed-dead-time

method is implemented in the SPS gate driver. The

fixed-dead-time circuitry monitors the internal HS signal

and adds a fixed delay long enough to gate on GL after

a desired tD_DEADOFF (~ 5 ns, tD_DEADOFF = tFD_OFF1),

regardless of SW node state.

Exiting 3-State Condition

When exiting a valid 3-state condition, the gate driver of

the FDMF5821 follows the PWM input command. If the

PWM input goes from 3-state to LOW, the low-side

MOSFET is turned on. If the PWM input goes from 3-

state to HIGH, the high-side MOSFET is turned on. This

is illustrated in Figure 29 below.

Inductor

Current

PWM

GH to SW

VIH_PWM

VIL_PWM

VTRI_HI

VTRI_LO

VIH_PWM

3-State

Window

VTRI_HI

VTRI_LO

VIH_PWM

VTRI_HI

VIL_PWM

10%

90%

10%

90%

10%

90%

10%

tPD_PHGLL

tD_DEADON

tPD_PLGHL

tD_DEADOFF

tPD_PHGLL

tD_DEADON2

tD_HOLD-OFF

tPD_THGHH

tPD_TLGLH

Less than

tD_HOLD-OFF

Less than

tD_HOLD-OFF

3-State

tHOLD_OFF

Window

3-State

tHOLD_OFF

Window

GL / GH

off

GL / GH

off

tD_HOLD-OFF

NOTES:

tPD_XXX = propagation delay from external signal (PWM, ZCD#, etc.) to IC generated signal. Example : tPD_PHGLL – PWM going HIGH to low-side MOSFET VGS (GL) going LOW

tD_XXX = delay from IC generated signal to IC generated signal. Example : tD_DEADON – low-side MOSFET VGS LOW to high-side MOSFET VGS HIGH

PWM

tPD_PHGLL = PWM rise to LS VGS fall, VIH_PWM to 90% LS VGS

tPD_PLGHL = PWM fall to HS VGS fall, VIL_PWM to 90% HS VGS

tPD_PHGHH = PWM rise to HS VGS rise, VIH_PWM to 10% HS VGS (ZCD# held LOW)

Exiting 3-State

tPD_TSGHH = PWM 3-State to HIGH to HS VGS rise, VIH_PWM to 10% HS VGS

tPD_TSGLH = PWM 3-State to LOW to LS VGS rise, VIL_PWM to 10% LS VGS

ZCD#

tPD_ZLGLL = ZCD# fall to LS VGS fall, VIL_ZCD# to 90% LS VGS

tPD_ZHGLH = ZCD# rise to LS VGS rise, VIH_ZCD# to 10% LS VGS

Dead Times

tD_DEADON = LS VGS fall to HS VGS rise, LS-Comp trip value to 10% HS VGS

tD_DEADOFF = SW fall to LS VGS rise, SW-Comp trip value to 10% LS VGS

Figure 29.

PWM HIGH / LOW / 3-State Timing Diagram

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