L9678P datasheet(124/203 Pages) STMICROELECTRONICS

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Remote sensor interface

L9678P, L9678P-S

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DocID029274 Rev 3

Remote sensor interface

The L9678P-S contains 2 remote sensor interfaces, capable of supporting PSI-5 protocol

(standard voltage range). A block diagram of the interface is shown below. The circuitry

consists of a power interface that demodulates current flowing in the external sensor and

transmits these current states to the decoder, which produces a digital value for each

satellite channel. Data are then output through the Remote Sensor Data Registers

(RSDRx). The power interface also contains error detection circuitry. When a fault is

detected, the error code is stored in a global SPI data buffer in the Remote Sensor Data

Registers (RSDRx).

Figure 30. Remote sensor interface logic blocks

The Remote Sensor Configuration Registers (RSCRx) allow for configuration of the

particular PSI5 protocol adopted by the sensor and the transceiver current limit blanking

time.

The Remote Sensor Control Register (RSCTRL) allows for interface channels to be

switched on and off via SPI.

RSU interface has 2 registers per channel, which can report either data or fault information,

that can be readout by sending 2 consecutive Read commands of the Remote Sensor Data

and the next SPI reading contains the most recent one. SPI accesses both from the same

address, i.e. the MCU should do 2 reads of the same RID to get both data samples. The

couple of registers will retain only the last two received messages, regardless they have

been qualified as valid or invalid data. In case of driver fault (Short to Ground, Short to

Battery, Over-current, Open detection, Over-temperature) any message is lost. To re-start a

correct reception of messages, it is needed to have no more fault present and fault flag read

by MCU.

If the device detects an error on the sensor interface, the fault bit in RSDRx (FLTBIT) will be

set to '1' and the following bits will be used to report the detected errors. Otherwise, the

are explained in the following sections.

When a fault condition is detected, the RSFLT bit of the global status word (GSW) is set to

1, except in the case the register is empty for which NODATA fault bit will be set instead.

Data are cleared upon reading the RSDRx register.

RSU interface is supplied by VSUP regulator as showed in Figure 31. To avoid a too low

RSU output voltage in case of battery loss, the upper VINGOOD and VBATMOND

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