CX28331 datasheet(20/68 Pages) CONEXANT

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1.0 Pin Description

CX28331/CX28332/CX28333

1.1 Pin Assignments

Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

1-10

Conexant

100985A

4, 5, 20, 21

12, 13

—

VDD

Power

Connect to 3.3 V power.

1, 8, 17, 24

9, 16

—

VSS

Ground

Connect to ground.

Miscellaneous

——

Power down for Ch1

Power down transceiver channel

0 = Power down channel (off)

1 = Channel active (on)

Note: A special power-down mode

exists when all three PDBs are set

low. This special mode shuts off the

entire chip (including biasing). This

is useful for static Idd testing.

—

PD1

—

PD2

Power down for Ch2

——

PD3

Power down for Ch3

——

REFCLK

Reference clock for Ch1

Reference clock from off-chip.

This clock should be set to one of

the following:

•

E3 rate (34.368 MHz)

•

DS3 rate (44.736 MHz)

•

STS-1 rate (51.84 MHz)

The clock rate should correspond to

the mode of operation that has been

chosen for the channel.

—

REFCLK1

—

REFCLK2

Reference clock for Ch2

——

REFCLK3

Reference clock for Ch3

RBIAS

Bias resistor

A 12.1 k

Ω ± 1% resistor tied from

this pin to ground provides the

current reference to the entire

chip.(2)

Reset

I/O

Asynchronous reset (reset entire

device).

GPD

Global Power down

I/O

Power down (Static Idd testing).

0 = Power down disable

1 = Power down active

2, 3, 6, 7, 18,

19, 22, 23,

25, 26, 27,

29, 30, 31,

32, 33, 34,

35, 36, 37,

38, 39, 40,

42, 61, 62,

63, 64, 65,

66, 67, 68,

69, 70, 71,

72, 74, 75,

10, 11, 14,

15, 42,

44–58

No connect

—

Not connected.

NOTE(S):

(1) This pin should be connected to 3.3 V in an all-3.3 V design.

(2) Placing a capacitor from this pin to ground may result in instabilities.

3. All digital input pins contain a 75 k

Ω pull-down resistor from input to DVSS.

Table 1-1. CX2833i-1x Pin Definitions (6 of 6)

Pin #

Signal Name

Description

I/O/P

Notes

CX28331-1x CX28332-1x CX28333-1x

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