CX28331 datasheet(30/68 Pages) CONEXANT

30 / 68 page

1.0 Pin Description

CX28331/CX28332/CX28333

1.1 Pin Assignments

Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

1-20

Conexant

100985A

——

REFCLK

Reference clock

for Ch1

Reference clock from off-chip.

This clock should be set to one of the

following:

•

E3 rate (34.368 MHz)

•

DS3 rate (44.736 MHz)

•

STS-1 rate (51.84 MHz)

The clock rate should correspond to the

mode of operation that has been chosen for

the channel.

—

REFCLK1

—

REFCLK2

Reference clock

for Ch2

——

REFCLK3

Reference clock

for Ch3

RBIAS

Bias resistor

A 12.1 k

Ω ± 1% resistor tied from this pin

to ground provides the current reference to

the entire chip.(2)

Reset

I/O

Asynchronous reset (reset entire device).

GPD

Global Power

down

I/O

Power down (Static Idd testing).

0 = Power down disable

1 = Power down active

——

TMONP

Ch1 positive

input

Transmit monitor input pins are normally

tied to their respective transmit line

outputs, i.e., (TMON1P

⇒ TLINE1P and

TMON1M

⇒ TLINE1M).

Loss of signal outputs are active high

when the monitor inputs detect no signal.

The TX monitor test pin will assert all

TLOS outputs when TMONTST is high.

This is used to test board level functionality

downstream from the TLOS outputs.

—

TMON1P

——

TMONM

Ch1 negative

input

—

TMON1M

—

TMON2P

Ch2 positive

input

—

TMON2M

Ch2 negative

input

——

TMON3P

Ch3 positive

input

——

TMON3M

Ch3 negative

input

——

TLOS

TX loss of signal

Ch1 Output

—

TLOS1

—

TLOS2

TX loss of signal

Ch2 Output

——

TLOS3

TX loss of signal

Ch3 Output

TMONTST

TX monitor test

Table 1-2. CX2833i-3x Pin Definitions (7 of 8)

Pin #

Signal Name

Description

I/O/P

Notes

CX28331-3x CX28332-3x CX28333-3x

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