PCI7510 datasheet(72/234 Pages) TI

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3–32

For example, load capacitors (C9 and C10 in Figure 3–21) of 16 pF each were appropriate for the layout of the

PCI7510 evaluation module (EVM), which uses a crystal specified for 12-pF loading. The load specified for the crystal

includes the load capacitors (C9 and C10), the loading of the PHY pins (CPHY), and the loading of the board itself

(CBD). The value of CPHY is typically about 1 pF, and CBD is typically 0.8 pF per centimeter of board etch; a typical

board can have 3 pF to 6 pF or more. The load capacitors C9 and C10 combine as capacitors in series so that the

total load capacitance is:

L +

C10

) C10 )

PHY ) CBD

24.576 MHz

CPHY + CBD

C10

Figure 3–21. Load Capacitance for the PCI7510 PHY

The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency, minimizing noise

introduced into the PHY phase-lock loop, and minimizing any emissions from the circuit. The crystal and two load

capacitors must be considered as a unit during layout. The crystal and the load capacitors must be placed as close

as possible to one another while minimizing the loop area created by the combination of the three components.

Varying the size of the capacitors may help in this. Minimizing the loop area minimizes the effect of the resonant

current (Is) that flows in this resonant circuit. This layout unit (crystal and load capacitors) must then be placed as

close as possible to the PHY X1 and X0 terminals to minimize etch lengths, as shown in Figure 3–22.

C10

For more details on crystal selection, see application report SLLA051 available from the TI website:

http://www.ti.com/sc/1394.

Figure 3–22. Recommended Crystal and Capacitor Layout

3.10.3 Bus Reset

In the PCI7510 device, the initiate bus reset (IBR) bit may be set to 1 in order to initiate a bus reset and initialization

sequence. The IBR bit is located in PHY register 1, along with the root-holdoff bit (RHB) and Gap_Count field, as

required by IEEE Std 1394a-2000. Therefore, whenever the IBR bit is written, the RHB and Gap_Count are also

written.

The RHB and Gap_Count may also be updated by PHY-config packets. The PCI7510 device is IEEE 1394a-2000

compliant, and therefore both the reception and transmission of PHY-config packets cause the RHB and Gap_Count

to be loaded, unlike older IEEE 1394-1995 compliant PHY devices which decode only received PHY-config packets.

The gap-count is set to the maximum value of 63 after 2 consecutive bus resets without an intervening write to the

Gap_Count, either by a write to PHY register 1 or by a PHY-config packet. This mechanism allows a PHY-config

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