PCI7510 datasheet(39/234 Pages) TI

39 / 234 page

2–20

Table 2–16. IEEE 1394 Physical Layer Terminals

TERMINAL

NAME

NUMBER

I/O

DESCRIPTION

NAME

PDV

GHK

I/O

DESCRIPTION

CNA

111

P17

I/O

Cable not active. This terminal is asserted high when there are no ports receiving incoming bias voltage.

If it is not used, then this terminal must be strapped either to GND through a resistor.

CPS

P10

Cable power status input. This terminal is normally connected to cable power through a 400-k

Ω resistor.

This circuit drives an internal comparator that is used to detect the presence of cable power. If CPS is

not used to detect cable power, then this terminal must be tied to ground.

FILTER0

FILTER1

105

106

T19

R17

I/O

PLL filter terminals. These terminals are connected to an external capacitance to form a lag-lead filter

required for stable operation of the internal frequency multiplier PLL running off of the crystal oscillator.

A 0.1-

µF ±10% capacitor is the only external component required to complete this filter.

PC0

PC1

PC2

V10

W10

P09

Power class programming inputs. On hardware reset, these inputs set the default value of the power

class indicated during self-ID. Programming is done by tying these terminals high or low.

W13

V13

–

Current-setting resistor terminals. These terminals are connected to an external resistance to set the

internal operating currents and cable driver output currents. A resistance of 6.34 k

Ω ±1% is required

to meet the IEEE Std 1394-1995 output voltage limits.

TPA0P

TPA0N

V12

W12

I/O

Twisted-pair cable A differential signal terminals. Board trace lengths from each pair of positive and

negative differential signal pins must be matched and as short as possible to the external load resistors

TPA1P

TPA1N

101

V15

W15

I/O

negative differential signal pins must be matched and as short as possible to the external load resistors

and to the cable connector.

TPBIAS0

TPBIAS1

103

U12

U15

I/O

Twisted-pair bias output. This provides the 1.86-V nominal bias voltage needed for proper operation

of the twisted-pair cable drivers and receivers and for signaling to the remote nodes that there is an

active cable connection. Each of these pins must be decoupled with a 1.0-

µF capacitor to ground.

TPB0P

TPB0N

V11

W11

I/O

Twisted-pair cable B differential signal terminals. Board trace lengths from each pair of positive and

negative differential signal pins must be matched and as short as possible to the external load resistors

TPB1P

TPB1N

V14

W14

I/O

negative differential signal pins must be matched and as short as possible to the external load resistors

and to the cable connector.

109

110

R18

R19

–

Crystal oscillator inputs. These pins connect to a 24.576-MHz parallel resonant fundamental mode

crystal. The optimum values for the external shunt capacitors are dependent on the specifications of

the crystal used (see Section 3.10.2, Crystal Selection). Terminal 5 has an internal 10-k

Ω (nominal

value) pulldown resistor. An external clock input can be connected to the XI terminal. When using an

external clock input, the XO terminal must be left unconnected. Refer to Section 3.10.2 for the operating

characteristics of the XI terminal.

Table 2–17. Power Supply Terminals

TERMINAL

NAME

NUMBER

I/O

DESCRIPTION

NAME

PDV

GHK

I/O

DESCRIPTION

ANALOGGND

U11

R12

R13

–

Analog circuit ground terminals.

ANALOGVCC

R11

U13

U14

–

Analog circuit power terminals. A parallel combination of high frequency decoupling capacitors near

each terminal is suggested, such as 0.1

µF and 0.001 µF. Lower frequency 10-µF filtering capacitors

are also recommended. These supply terminals are separated from VDPLL and VSPLL internal to

the device to provide noise isolation. They must be tied at a low-impedance point on the circuit board.

VDPLL

107

P15

–

PLL circuit power terminals. A parallel combination of high frequency decoupling capacitors near the

terminal is suggested, such as 0.1

µF and 0.001 µF. Lower frequency 10-µF filtering capacitors are

also recommended. This supply terminal is separated from AVDx internal to the device to provide

noise isolation. It must be tied at a low-impedance point on the circuit board.

VSPLL

108

N14

–

PLL circuit ground terminals. This terminal must be tied to the low-impedance circuit board ground

plane.

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