18

LTC4007

4007i

Figure 11. Circuit Application (16.8V/3A) to Automatically Trickle Charge Depleted Batteries

3C4C

CHEM

LOBAT

ACP

SHDN

FAULT

CHG

FLAG

NTC

LOBAT

ACP

SHDN

FAULT

CHG

FLAG

DCIN

INFET

CLP

CLN

TGATE

BGATE

PGND

CSP

BAT

PROG

ITH

GND

LTC4007

R9 32.4k 1%

309k

1%

C7

0.47

µF

THERMISTOR

TIMING RESISTOR

(~2 HOURS)

R12

100k

R11

100k

R10

100k

*

*

DCIN

0V TO 20V

3A

C1

0.1

µF

Q3

INPUT SWITCH

C4

15nF

Q1

Q2

D1

C2

20

µF

L1

15

µH 3A

R1

4.9k

1%

R4

3.01k

1%

R5 3.01k 1%

0.033

Ω

1%

0.033

Ω

1%

C3

20

µF

*PIN OPEN

D1: MBRM140T3

Q1: Si4431ADY

Q2: FDC645N

Q4: 2N7002 OR BSS138

BAT

MONITOR

(CHARGING

CURRENT

MONITOR)

SYSTEM

LOAD

C6

0.12

µF

R7

6.04k

1%

R14

73.2k

1%

C5

0.0047

µF

4007 F11

R6

26.7k

1%

Q4

5. Place output capacitors next to the sense resistor

output and ground.

6. Output capacitor ground connections need to feed

into same copper that connects to the input capacitor

ground before tying back into system ground.

General Rules

7. Connection of switching ground to system ground or

internal ground plane should be single point. If the

system has an internal system ground plane, a good

way to do this is to cluster vias into a single star point

to make the connection.

8. Route analog ground as a trace tied back to IC ground

(analog ground pin if present) before connecting to

any other ground. Avoid using the system ground

plane. CAD trick: make analog ground a separate

ground net and use a 0

Ω resistor to tie analog ground

to system ground.

9. A good rule of thumb for via count for a given high

current path is to use 0.5A per via. Be consistent.

10. If possible, place all the parts listed above on the same

PCB layer.

11. Copper fills or pours are good for all power connec-

tions except as noted above in Rule 3. You can also use

copper planes on multiple layers in parallel too—this

helps with thermal management and lower trace in-

ductance improving EMI performance further.

12. For best current programming accuracy provide a

Figure 12 as an example.

CSP and BAT pins to a minimum. The traces connecting

these pins to their respective resistors should be as short

as possible.

APPLICATIO S I FOR ATIO