LP87332D datasheet(32/74 Pages) TI1

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LP87332D

SNVSAU6 – NOVEMBER 2017

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In buck regulator short-circuit and overload situations the BUCKx_SC_INT bit in INT_BUCK register and the

INT_BUCKx bit in INT_TOP_1 register are set to 1, the BUCKx_STAT bit in BUCK_STAT register is set to 0, and

the nINT signal is pulled low. In LDO regulator short-circuit and overload situations the LDOx_SC_INT bit in

INT_LDO register and the INT_LDOx bit in INT_TOP_1 register are set to 1, the LDOx_STAT bit in LDO_STAT

BUCKx_SC_INT or to the LDOx_SC_INT bit. Upon clearing the interrupt the regulator makes a new start-up

attempt if the regulator is in an enabled state.

7.3.8.3.2

Overvoltage Protection

The LP87332D device monitors the input voltage from the VANA pin in standby and active operation modes. If

the input voltage rises above VANAOVP voltage level, all the regulators are disabled immediately (without

switching ramp, no shutdown delays), pulldown resistors discharge the output voltages if they are enabled

(BUCKx_RDIS_EN = 1 in BUCKx_CTRL_1 register and LDOx_RDIS_EN = 1 in LDOx_CTRL register), GPOs are

set to logic low level, nINT signal is pulled low, OVP_INT bit in INT_TOP_1 register is set to 1, and

BUCKx_STAT bit in BUCK_STAT register and LDOx_STAT bit in LDO_STAT register are set to 0. The host

processor clears the interrupt by writing 1 to the OVP_INT bit. If the input voltage is above overvoltage detection

level the interrupt is not cleared. The host can read the status of the overvoltage from the OVP_STAT bit in

TOP_STAT register. Regulators cannot be enabled as long as the input voltage is above overvoltage detection

level or the overvoltage interrupt is pending.

7.3.8.3.3

Thermal Shutdown

The LP87332D has an overtemperature protection function that operates to protect itself from short-term misuse

and overload conditions. When the junction temperature exceeds around 150°C, the regulators are disabled

immediately (without switching ramp, no shutdown delays), the TDIE_SD_INT bit in INT_TOP_1 register is set to

1, the nINT signal is pulled low, and the device enters STANDBY. nINT is cleared by writing 1 to the

TDIE_SD_INT bit. If the temperature is above thermal shutdown level the interrupt is not cleared. The host can

read the status of the thermal shutdown from the TDIE_SD_STAT bit in TOP_STAT register. Regulators cannot

be enabled as long as the junction temperature is above thermal shutdown level or the thermal shutdown

interrupt is pending.

7.3.8.4 Fault (Power Down)

7.3.8.4.1

Undervoltage Lockout

When the input voltage falls below VANAUVLO at the VANA pin, the buck and LDO regulators are disabled

immediately (without switching ramp, no shutdown delays), and the output capacitor is discharged using the

pulldown resistor, and the LP87332D device enters SHUTDOWN. When V(VANA) voltage is above VANAUVLO

threshold level, the device powers up to STANDBY state.

If the reset interrupt is unmasked by default (OTP bit for RESET_REG_MASK is 0 in TOP_MASK_2 register) the

RESET_REG_INT interrupt bit in INT_TOP_2 register indicates that the device has been in SHUTDOWN. The

host processor must clear the interrupt by writing 1 to the RESET_REG_INT bit. If the host processor reads the

RESET_REG_INT interrupt bit after detecting an nINT low signal, it knows that the input supply voltage has been

below VANAUVLO level (or the host has requested reset with SW_RESET bit in RESET register), and the

registers are reset to default values.

7.3.9 Operation of the GPO Signals

The LP87332D device supports up to 2 general purpose output signals, GPO and GPO2. The GPO2 signal is

multiplexed with CLKIN signal. The selection between CLKIN and GPO2 pin function is set with CLKIN_PIN_SEL

bit in CONFIG register.

The GPO pins are configured with the following bits:

•

GPOx_OD bit in GPO_CTRL register defines the type of the output, either push-pull with V(VANA) level or open

drain

The logic level of the GPOx pin is set by EN_GPOx bit in GPO_CTRL register.

The control of the GPOs can be included to start-up and shutdown sequences. The GPO control for a sequence

with EN pin is selected by GPOx_EN_PIN_CTRL bit in GPO_CTRL register. For start-up and shutdown

sequence control see Enable and Disable Sequences.

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