SLG46721 datasheet(32/101 Pages) DIALOG

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000-0046721-114

Page 31 of 100

SLG46721

8.1 Matrix Input Table

Table 24. Matrix Input Table

Matrix Input Signal Function

Matrix Decode

VSS

000

pin2 digital input

pin3 digital input

pin4 digital input

pin5 digital input

pin6 digital input

pin7 digital input

pin8 digital input

pin9 digital input

pin10 digital input

ACMP_0 output

ACMP_1 output

ACMP_2 output

CNT_DLY0(14bit) output

CNT_DLY1(14bit with ext CK/Reset) output

CNT_DLY4(8 bit) output

CNT_DLY5(8 bit) output

CNT_DLY6(8 bit) output

ACMP_3 output

Inverting of DFF/LATCH_2 output

VSS (spare)

Inverting of DFF/LATCH_3 output

LUT4_0 output (CNT_DLY2 output (8 bit w/ ext CK,reset))

LUT4_1 output (CNT_DLY3 output (8 bit w/ ext CK,reset))

LUT3_0 output

LUT3_1 output

LUT3_2 output (DFF/LATCH_2 output with resetb or setb)

LUT3_3 output (DFF/LATCH_3 output with resetb or setb)

LUT3_4 output

LUT3_5 output

LUT3_6 output

LUT3_7 output

LUT3_8 output(1st stage pipe 1 delay output)

LUT2_0 output (DFF/LATCH_4 output)

100

LUT2_1 output (DFF/LATCH_5 output)

100

LUT2_2 output (DFF/LATCH_6 output)

100

LUT2_3 output (DFF/LATCH_7 output)

100

LUT2_4 output

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