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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SLG46721 датащи(PDF) 72 Page - Dialog Semiconductor |
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SLG46721 датащи(HTML) 72 Page - Dialog Semiconductor |
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72 / 101 page  000-0046721-114 Page 71 of 100 SLG46721 15.0 Programmable Delay / Edge Detector The SLG46721 has a programmable time delay logic cell available that can generate a delay that is selectable from one of four timings (time1) configured in the GreenPAK Designer. The programmable time delay cell can generate one of four different delay patterns, rising edge detection, falling edge detection, both edge detection and both edge delay. These four patterns can be further modified with the addition of delayed edge detection, which adds an extra unit of delay as well as glitch rejection during the delay period. See the timing diagrams below for further information. Note : The input signal must be longer than the delay, otherwise it will be filtered out. 15.1 Programmable Delay Timing Diagram - Edge Detector Output Figure 32. Programmable Delay Figure 33. Edge Detector Output Programmable Delay OUT IN reg <966:965> From Connection Matrix Output <74> To Connection Matrix Input <44> reg <968:967> reg <969> Delayed Edge Detector Output Edge Mode Selection Delay Value Selection time1 Edge Detector Output IN Rising Edge Detector Falling Edge Detector Both Edge Detector Both Edge Delay time1 time1 can be set by register |
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