AD5337ARM datasheet(6/24 Pages) AD

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AD5337/AD5338/AD5339

Rev. A | Page 6 of 24

TIMING CHARACTERISTICS

VDD = 2.5 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.

Table 3.

Parameter

Limit at TMIN, TMAX

(A and B Versions)

Unit

Conditions/Comments

fSCL

400

kHz max

SCL clock frequency

2.5

µs min

SCL cycle time

0.6

µs min

tHIGH, SCL high time

1.3

µs min

tLOW, SCL low time

0.6

µs min

tHD, STA, start/repeated start condition hold time

100

ns min

tSU, DAT, data setup time

t61

0.9

µs max

tHD, DAT, data hold time

µs min

tHD, DAT, data hold time

0.6

µs min

tSU, STA, setup time for repeated start

0.6

µs min

tSU, STO, stop condition setup time

1.3

µs min

tBUF, bus free time between a stop and a start condition

t10

300

ns max

tR, rise time of SCL and SDA when receiving

ns min

tR, rise time of SCL and SDA when receiving (CMOS-compatible)

t11

250

ns max

tF, fall time of SDA when transmitting

ns min

tF, fall time of SDA when receiving (CMOS-compatible)

300

ns max

tF, fall time of SCL and SDA when receiving

20 + 0.1 CB2

ns min

tF, fall time of SCL and SDA when transmitting

400

pF max

Capacitive load for each bus line

1 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to VIH min of the SCL signal) in order to bridge the undefined region of SCL’s

falling edge.

2 CB is the total capacitance of one bus line in pF; tR and tF measured between 0.3 VDD and 0.7 VDD.

STOP

SCL

SDA

START

CONDITION

t11

t10

REPEATED

START

CONDITION

Figure 2. 2-Wire Serial Interface Timing Diagram

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