LM2753SD datasheet(4/8 Pages) NSC

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Electrical Characteristics

(Notes 2, 7) (Continued)

Note 5: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be

derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operationg junction temperature (TJ-MAX-OP = 120

oC), the maximum power

dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the

following equation: TA-MAX =TJ-MAX-OP -(θJA xPD-MAX).

Note 6: Junction-to-ambient thermal resistance (

θJA) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the JEDEC

standard JESD51-7. The test board is a 4 layer FR-4 board measuring 102mm x 76mm x 1.6mm witha2x1 array of thermal vias. The ground plane on the board

is 50mm x 50mm. Thickness of copper layers are 36µm/18µm /18µm/36µm (1.5oz/1oz/1oz/1.5oz). Ambient temperature in simulation is 22˚C, still air. Power

dissipation is 1W.

The value of

θJA of the LM2753 in LLP-10 could fall in a range as wide as 50oC/W to 150oC/W (if not wider), depending on PWB material, layout, and environmental

conditions. In applications where high maximum power dissipation exists (high VIN, high IOUT), special care must be paid to thermal dissipation issues. For more

information on these topics, please refer to Application Note 1187: Leadless Leadframe Package (LLP) and the Power Efficiency and Power Dissipation

section of this datasheet..

Note 7: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.

Note 8: CIN,COUT, and C1 : Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics

Note 9: Turn-on time is measured from when the EN signal is pulled high until the output voltage on VOUT crosses 90% of its final value.

Note 10: Flash Turn-on time is measured from when the FLASH signal is pulled high until the voltage on IOUT crosses 90% of its final programmed value.

Block Diagram

20140606

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