CS5954AM
ADVANCE
INFORMATION
Document #: 38-08025 Rev. **
Page 19 of 44
4.13.3
Extended Page 1 Map Register (0xC018: R/W)
This register contains the Page 1 high order address bits. These bits are always appended to accesses to the Page 1 Memory
mapped space. The default is 0x0000.
D7–oA20–13
Page 1 high order address bits. The address pins on A21–A13 will reflect the content of
this register when CS5954AM accesses the address 0x8000–0x9FFF.
4.13.4
Extended Page 2 Map Register (0xC01A: R/W)
This register contains the Page 2 high order address bits. These bits are always appended to accesses to the Page 2 Memory
mapped space. The default is 0x0000.
D7–oA20–13
Page 2 high order address bits. The address pins on A21–A13 will reflect the content of
this register when CS5954AM access the address 0xA000–0xBFFF.
4.13.5
Memory Map
The total memory space allocated by the CS5954AM is 64K-bytes. Program, data, and I/O space are contained within a 64K-byte
address space. The program code or data can be stored in either external RAM or external ROM.
The CS5954AM Controller provides a 16-bit Memory interface that can support a wide variety of external, RAM and ROM devices.
The CS5954AM Controller memory space is byte addressable and is divided as shown in Table 4-5.
Each External memory space can be 8 or 16 bits wide, and can be programmed to have up to seven wait-states.
Notes:
19. The External RAM address from 0x0000 to 0x0C00 will not be accessible from the CS5954AM processor. This is an overlay memory space between internal
RAM and external RAM. The addressable external RAM will occupy from 0x0C00–0x7FFF, which is 29 Kbyte. The signal name nXRAMSEL on CS5954AM–pin56
will be active when the CPU access address from 0x0C00–0x7FFF.
20. When bit 12 (ROM Merge Bit) of the Extended Memory Controller Register at address 0xC03A is “0,” then the External ROM address space will be mapped
from 0xC100–0xE7FF. The address from 0x8000–0xC100 and the address from 0xE800 to 0xFFFF are the overlay memory spaces. The actual total size of the
external ROM will be (0xE800–0xC100), which is 9.75 Kbyte. The signal nXROMSEL on the CS5954AM (pin 57) will be active when the CPU accesses the
address from 0xC100–0xE7FF. The signal nXMEMSEL on the CS5954AM (pin 58) will be active when the CPU accesses the address from 0x8000–0xBFFF.
When bit 12 (ROM Merge Bit) of the Extended Memory Controller Register at address 0xC03A is “1,” then the External ROM address space will be mapped into
these windows: 0x8000–0xBFFF and 0xC100–0xE7FF. The address from 0xC000 to 0xC100 and the address from 0xE800–0xFFFF are the overlay memory
spaces. The actual total size of the external ROM will be (0xC000–0x8000) and (0xE800–0xC100), which is 16 Kbyte + 9.75 Kbytes, or 25.75K.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
000000
0
0
A20
A19
A18
A17
A16
A15
A14
A13
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
A20
A19
A18
A17
A16
A15
A14
A13
Table 4-5. Memory Map
Function
Address
Internal RAM
0x0000–0x0BFF
External RAM
0x0C00–0x7FFF[19]
Memory Mapped Registers
0xC000–0xC0FF
External ROM
0xC100–0xE7FF[20]
Internal ROM
0xE800–0xFFFF
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