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CS5954AM
ADVANCE
INFORMATION
Document #: 38-08025 Rev. **
Page 39 of 44
9.9
CS5954AM SRAM Read Cycle
Notes:
46. 0 wait state cycle.
47. tAC means at 0 wait states, with PCLK = 2/3 RCLK, the SRAM access time should be 12 ns max. For a 1-wait state cycle, with PCLK = 2/3 RCLK, the SRAM
access time should be at 12 + 31ns = 43 ns max. See register 0xC006 description for PCLK information.
Parameter
Description
Min.
Typical
Max.
tclk
Clock Period (48 MHz)
20.0 ns
20.8 ns
thigh
Clock HIGH Time
9 ns
11 ns
tlow
Clock LOW Time
9 ns
11 ns
trise
Clock Rise Time
5.0 ns
tfall
Clock Fall Time
5.0 ns
Duty Cycle
–5%
+5%
Parameter
Description
Min.
Typical
Max.
tCR
CS LOW to RD LOW
1 ns
tRDH
RD HIGH to data hold
5 ns
tCDH
CS HIGH to Data Hold
3 ns
tRPW
[46]
RD LOW Time
28 ns
31 ns
tAR
RD LOW to Address Valid
1 ns
3 ns
tAC
[47]
RAM Access to Data Valid
12 ns
Address
CS
RD
Din
tAR
tRPW
Data Valid
tCR
tAC
tRDH
tCDH
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