AD9260AS datasheet(34/45 Pages) AD

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AD9260

Rev. C | Page 33 of 44

POWER DISSIPATION CONSIDERATIONS

The power dissipation of the AD9260 is dependent on its

application specific configuration and operating conditions.

The analog power dissipation as shown in Figure 70 is primarily

a function of its power bias setting and sample rate. It remains

insensitive to the particular input waveform being digitized or

digital filter MODE setting. The digital power dissipation is

primarily a function of the digital supply setting (i.e., +3 V to

+5 V), the sample rate and, to a lesser extent, the MODE setting

and input waveform. Figure 71 and Figure 72 show the total

current dissipation of the combined digital (DVDD) and digital

driver supply (DRVDD) for +3 V and +5 V supplies. Note,

DVDD and DRVDD are typically derived from the same supply

bus since no degradation in performance results. A 1 MHz full-

scale sine wave was used to ensure maximum digital activity in

the digital filters and the digital drivers had a fanout of one.

Note also that a twofold decrease in digital supply current

results when the digital supply is reduced form +5 V to +3 V.

110

130

SAMPLE RATE (MSPS)

515

QUARTER BIAS [8k

Ω]

FULL BIAS [2k

Ω]

HALF BIAS [4k

Ω]

Figure 70. IAVDD vs. Sample Rate (AVDD = +5V, Mode 1x-4x)

SAMPLE RATE (MSPS)

× MODE

Figure 71. IDVDD/IDRVDD vs. Sample Rate (DVDD = DRVDD = 3 V,

fIN = 1 MHz)

SAMPLE RATE (MSPS)

515

× MODE

Figure 72. IDVDD/IDRVDD vs. Sample Rate (DVDD = DRVDD = 5 V, fIN = 1

MHz)

DIGITAL OUTPUT DRIVER CONSIDERATIONS

(DRVDD)

The AD9260 output drivers can be configured to interface with

+5 V or 3.3 V logic families by setting DRVDD to +5 V or 3.3 V,

respectively. The AD9260 output drivers in each mode are

appropriately sized to provide sufficient output current to drive

a wide variety of logic families. However, large drive currents

tend to cause glitches on the supplies and may affect SINAD

performance. Applications requiring the AD9260 to drive large

capacitive loads or large fanout may require additional

decoupling capacitors on DRVDD. The addition of external

buffers or latches helps reduce output loading while providing

effective isolation from the data bus.

Clock Input and Considerations

The AD9260 internal timing uses the two edges of the clock

input to generate a variety of internal timing signals. The clock

input must meet or exceed the minimum specified pulse width

high and low (tCH and tCL) specifications for the given A/D as

defined in the Switching Specifications at the beginning of the

data sheet to meet the rated performance specifications. For

example, the clock input to the AD9260 operating at 20 MSPS

may have a duty cycle between 45% and 55% to meet this

timing requirement since the minimum specified tCH and tCL is

22.5 ns. For clock rates below 20 MSPS, the duty cycle may

deviate from this range to the extent that both tCH and tCL are

satisfied. All high speed, high resolution A/Ds are sensitive to

the quality of the clock input. The degradation in SNR at a

given full-scale input frequency (fIN) due to only aperture jitter

(tA) can be calculated with the following equation:

(

)

[

]

IN t

SNR

log

In the equation, the rms aperture jitter, tA, represents the

rootsum square of all the jitter sources which include the clock

input, analog input signal, and A/D aperture jitter specification.

For example, if a 500 kHz full-scale sine wave is sampled by an

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