STV3550 datasheet(118/144 Pages) STMICROELECTRONICS

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STV3550

Parity may be odd or even, depending on the ParityOdd bit in the ASC_n_Control register. If the

modulo 2 sum of the eight data bits is 1, then the even parity bit will be set and the odd parity bit will

be cleared. The parity error flag (ParityError) will be set if a wrong parity bit is received. The parity

error flag is stored in the 9th bit (D8) of the ASC_n_RxBuffer register. The parity error bit is set high

if there is a parity error.

In wake-up mode, received frames are only transferred to the receive buffer register if the ninth bit

(the wake-up bit) is 1. If this bit is 0, no receive interrupt request will be activated and no data will be

transferred.

This feature may be used to control communication in multi-processor systems. When the master

processor wants to transmit a block of data to one of several slaves, it first sends out an address

byte which identifies the target slave. An address byte differs from a data byte in that the additional

ninth bit is a 1 for an address byte and a 0 for a data byte, so no slave will be interrupted by a data

byte. An address byte will interrupt all slaves (operating in 8-bit data plus wake-up bit mode), so

each slave can examine the 8 least significant bits (LSBs) of the received character, which is the

address. The addressed slave will switch to 9-bit data mode, which enables it to receive the data

bytes that will be coming (with the wake-up bit cleared). The slaves that are not being addressed

remain in 8-bit data plus wake-up bit mode, ignoring the data bytes which follow.

7.8.3

Transmission

Transmission begins at the next baud rate clock tick, provided that the Run bit is set and data has

been loaded into the ASC_n_TxBuffer. If the CTSEnable bit is set in the ASC_n_Control register

then transmission only occurs when CTS is high.

The transmitter empty flag (TxEmpty) indicates whether the output shift register is empty. It will be

set at the beginning of the last data frame bit that is transmitted, i.e. during the first system clock

cycle of the first stop bit shifted out of the transmit shift register.

The loop-back option (selected by the LoopBack bit of the ASC_n_Control register) internally

connects the output of the transmitter shift register to the input of the receiver shift register. This

may be used to test serial communication routines at an early stage without having to provide an

external network.

7.8.3.1 Transmission with FIFOs Enabled

The FIFOs are enabled by setting the FifoEnable bit of the ASC_n_Control register. The output

FIFO is implemented as a 16-deep array of 9-bit vectors. Values to be transmitted are written to the

output FIFO by writing to ASC_n_TxBuffer.

The TxFull bit of the ASC_n_Status register is set when the transmit FIFO is considered full, i.e.

when it contains 16 characters. Further writes to ASC_n_TxBuffer will fail to overwrite the most

Figure 72: 9-bit Tx Data Frame Format

start

bit

9th

bit

(LSB)

1st

stop

bit

2nd

stop

bit

• Data bit (D8)

• Parity bit

• Wake-up bit

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