STV3550 datasheet(114/144 Pages) STMICROELECTRONICS

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STV3550

The arbitration scheme does not affect the data transmitted by the winning master. Consequently,

arbitration proceeds concurrently with data transmission and valid data will have been received by

the selected slave during the arbitration process.

It is possible that the winning master is actually addressing the losing master and hence this device

must respond as if it were a slave device.

Arbitration is implemented in hardware by comparing the transmitted and received data bits every

cycle.

Loss of arbitration is indicated by the setting of the SSCARBL, arbitration lost error flag in the status

Loss of arbitration also causes a clock stretch to be inserted. The interrupt and the clock stretch will

occur immediately after the 8 bits plus acknowledge.

The arbitration lost status and interrupt will be cleared by a read of the status register.

The clock stretch is cleared when the software writes to the transmit buffer.

7.7.25 I²C Timing Specification

The I²C specification defines a number of timing constraints which must be met on the output clock

and data pins. The key values which must be met are described in Table 24.

Table 24: Key I²C Timing Requirements

Parameter

MIN

MAX

SCL Clock Frequency

100KHZ or 400KHz1

1. In FAST Mode

Hold Time of SCL after SDA START or REPSTART Condition.

After this time the first clock low pulse is created

1.0us or

0.6us

LOW Period of the SCL clock

4.7us or

1.3us

HIGH period of the SCL clock

4.0us or

0.6us

SDA Set-up time relative to SCL for a repeated START condition

4.6us or

0.6us

SDA Data Hold Time relative to SCL

300ns2

2. Actual requirement is 0ns but hold time must be at least 300ns on SDA line to comply with

uncertain period of max fall time of 300ns on the SCL line.

SDA Data Setup Time relative to SCL

250ns or

100ns3

Rise time of SDA and SCL lines

20+0.1Cb

100ns or 300ns

Fall time of SDA and SCL lines

20+0.1Cb

300ns

SDA Setup time relative to SCL for a STOP condition

4.0us or

0.6us

Capacitive load of each bus line (Cb)

400pF

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