AD9518-3 Summary

This document outlines key specifications for the AD9518-3, a high-performance PLL (Phase-Locked Loop) device.

1. Core Functionality:

️· PLL Device: Provides a flexible PLL solution for various applications.
️· Digital Lock Detect: Offers a digital lock detect function for reliable locking.
️· Programmability: Many parameters (including divider values, delay, ABP values, lock detect thresholds) are programmable via registers.

2. Key Specifications (Electrical):

️· Prescaler Input Frequency Range: 100 MHz to 3000 MHz
️· PLL Divider Delays: Programmable delays (0 - 11 phases) from 330ps to 990ps.
️· Charge Pump Current (ICP):
- Sink/Source: 4.8 mA
- Accuracy: 2.5%
- Programmable
️· Digital Lock Detect Window
- Low Range ABP: 3.5ns to 7.5ns.
- High Range ABP: 3.5ns to 15ns.

3. Noise Performance:

️· PLL In-Band Phase Noise (depends on configuration, e.g., PFD frequency, divider value)
- At 500 kHz PFD Frequency: -165 dBc/Hz
- At 1 MHz PFD Frequency: -162 dBc/Hz
- At 10 MHz PFD Frequency: -151 dBc/Hz
- At 50 MHz PFD Frequency: -143 dBc/Hz
️· Figure of Merit (FOM): ~ -220 dBc/Hz (approximate)

4. Programmable Features & Register Information:

️· PLL Divider: Values are controlled by software.
️· ABP (Active Bandwidth Pulse) Selection: Configurable via Registers 0x017[1:0] and 0x018[4] (Low/High Range settings).
- ABP ranges 1.3ns-2.9ns, 6.0ns
️· Register 0x017[1:0]: Selects ABP Low/High settings.
️· Register 0x018[4]: Selects ABP setting.
️· Register 0x019[5:3]: Programmable Delays

5. Critical Notes/Considerations:

️· Digital Lock Detect Requirement: The PFD frequency period must be longer than the unlock-after-lock time to ensure reliable operation.
️· Self-Bias Offset: REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input.
️· Noise Performance Dependence: Noise performance is dependent on the settings.