2-692
RF6100-1
Rev A0 031219
Pin
Function
Description
Interface Schematic
1VREG
Regulated voltage supply for amplifier bias. In Power Down mode, both
VREG and VMODE need to be LOW (<0.5V).
2VMODE
For nominal operation (High Power Mode), VMODE is set LOW. When
set HIGH, devices are biased lower to improve efficiency.
3GND
Ground connection. Connect to package base ground. For best perfor-
mance, keep traces physically short and connect immediately to
ground plane.
4RF IN
RF input internally matched to 50
Ω. This input is internally AC-coupled.
5VCC1
First stage collector supply. A low frequency decoupling capacitor
(e.g., 4.7
µF) may be required.
6VCC2
Output stage collector supply. A low frequency decoupling capacitor
(e.g., 4.7
µF) is required.
7GND
Ground connection. Connect to package base ground. For best perfor-
mance, keep traces physically short and connect immediately to
ground plane.
8RF OUT
RF output internally matched to 50
Ω. This output is internally
AC-coupled.
9GND
Ground connection. Connect to package base ground. For best perfor-
mance, keep traces physically short and connect immediately to
ground plane.
10
GND
Ground connection. Connect to package base ground. For best perfor-
mance, keep traces physically short and connect immediately to
ground plane.
Pkg
Base
GND
Ground connection. The backside of the package should be soldered to
a top side ground pad which is connected to the ground plane with mul-
tiple vias. The pad should have a short thermal path to the ground
plane.
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
