MN85571AC

13

SDD00023AEM

s Interfaces (continued)

2. DMA transfer interface (DIF)

The DMA transfer interface (DIF) transfers data using DMA between the external host and this device’s DMA data

transfer buffer memory (WRDM). Since WRDM has a size of 1 024 32-bit words, the maximum valid data count is

2 048.

(This function is valid when the CHIPCTL0 direct addressing access register dmasel bit is 0.)

The WRDM can be accessed in two ways: by read or write instructions from the SRISC and by DMA data transfers

(read or write) from the external host.

Since there are two techniques, which technique gains access is arbitrated by the DIF internal arbitration circuit.

Access requests to the arbitration circuit are issued from the SRISC by instruction execution, and from the external

host by writing a 1 to the DIFACC (HA[3:0] = $A) req register (a direct addressing register). If requests are issued to

the arbitration circuit at the same time, access permission is granted according to the priority determined by the value

of the difreg ($0020) indirect addressing access register.

Note that there are two DMA transfer modes: “single bus cycle DMA transfer mode”, in which access is

synchronized with the DMA clock signal (DMACLK), and “two bus cycle DMA transfer mode”, in which transfers

are not dependent on a clock signal.

3. Code output interface

The code output interface is provided to transfer data to a communication system or to the storage system media and

outputs a multiplexed AV bit stream to external circuits.

There are two major classes of output formats provided by the code output interface: “standalone mode (8-bit

parallel)”, which outputs the bit stream using a dedicated set of pins, and “DMA transfer mode (16-bit parallel) which

outputs using an external host bus shared with the host interface.

The setting of the CHIPCTL0 dma sel register (a direct addressing register) selects which of these two output formats

is used. If this bit is set to 0, standalone mode is used, and if set to 1, DMA transfer mode is used.

Additionally, there are three clock modes in standalone mode. These consist of two modes that use a code output clock

(RCLKI) input to this device, “inverted clock input standalone mode”, and “noninverted clock input standalone mode

as well as a mode that uses a code output clock (RCLKO) output from this device, “ARIB parallel interface standard

mode (TS output)”.

Also note that there are two DMA transfer modes which differ in the number of bus cycles required to transfer data,

“single bus cycle DMA transfer mode” and “two bus cycle DMA transfer mode”.

The table below summarizes these modes, and lists the clock frequencies, pins, and other items used in each mode.

Note that in every one of these modes, the maximum amount of valid output data per single handshake operation is

2 048 bytes, and that the maximum average output bit rate is 15 Mbps.

Mode

Pin names used

Clock frequencies

Output data format

Standalone

Inverted/noninverted

CDO[7:0], CDREADY,

RCLKI

MSB

mode

clock input

16 MHz maximum

first

ARIB parallel

CDO[7:0], CDREADY,

RCLKO

MSB

interface standard

6.75 MHz, 3.375 MHz

first

DMA

Single bus cycle

HD[15:0], NHDREQ,

DMACLK

Big Endian/

transfer

NHDACK, DMACLK

33 MHz maximum

Little Endian

mode

Two bus cycle

HD[15:0], NHCS, HA[3:0],

Clock signal not

Big Endian/

NHRE, NHWE, NHDREQ

required

Little Endian