Datasheet

MLX90255BA

Linear Optical Array

MLX90255BA Linear Optical Array

Page 1

Rev 1.2 08-Aug-01

3901090255

Features and Benefits

128 x 1 Sensor-Element Organization (1 Not Connected, 1 dummy, 128 real, 1 dummy

and 1 Dark Pixel)

385 Dots-Per-Inch (DPI) Sensor Pitch

High Linearity and Uniformity for 256 Gray-Scale (8-Bit) Applications

High Sensitivity: 1.7V @ 10µW/cm² @ 0.7ms integration time

Special Gain Compensation for use with single LED light source

Output Referenced to Ground

Low Image Lag

Single 5V Supply

Replacement for Texas Instruments TSL1301 & TSL1401 and MLX90255AA

Operation to 1MHz

Applications

Position Sensing

Electrical Power Assist Steering (EPAS)

Spectrometer Applications

Ordering Information

Part No.

Temperature Suffix

Package

Option

Temperature Range

MLX90255

K

LA

-BA

-40°C to 125°C Automotive

MLX90255

K

JA

-BA

-40°C to 125°C Automotive

Functional Diagram

3

5

Pixel 2

Pixel 1

Pixel 132

2

1

4

Hold

Q1

Q2

Q132

Switching Logic

132-Bit Shift Register

Integrator Reset

Sample

External

Load

Description

The MLX90255BA linear sensor array consists

of a 128 x 1 array of photodiodes, associated

charge amplifier circuitry and a pixel data-hold

function that provides simultaneous-integration

start and stop times for all pixels. The pixels

measure 200µm (H) by 66 µm (W) and 8 µm

spacing between pixels. Operation is simplified

by internal control logic that requires only a

serial-input (SI) signal and a clock.

The sensor consists of 128 photodiodes

arranged in a linear array. Light energy falling on

a photodiode generates photocurrent, which is

integrated by the active integration circuitry

associated with that pixel. During the integration

period, a sampling capacitor connects to the

output of the integrator through an analog

switch. The amount of charge accumulated at

each pixel is directly proportional to the light

intensity and the integration time. The output

and reset of the integrators is controlled by a

132-bit shift register and reset logic. An output

cycle is initiated by clocking in a logic 1 on SI.

This causes all 132 sampling capacitors to be

disconnected from their respective integrators

and starts an integrator reset period.

(continued on page 4)