TSB41BA3AIPFP datasheet(39/66 Pages) TI

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TSB41BA3A

IEEE 1394b THREEPORT CABLE TRANSCEIVER/ARBITER

SLLS618B − JUNE 2004 − REVISED AUGUST 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION (1394a-2000 INTERFACE)

LLC service request (continued)

NOTE:

The TSB41BA3A accepts a bus request with an invalid speed code and processes the bus request

normally. However, during packet transmission for such a request, the TSB41BA3A ignores any

data presented by the LLC and transmits a null packet.

For a read register request, the length of the LREQ bit stream is 9 bits as shown in Table 17.

Table 17. Read Register Request

BIT(s)

NAME

DESCRIPTION

Start bit

Indicates the beginning of the transfer (always 1)

1−3

Request type

A 100 indicating this is a read register request.

4−7

Address

Identifies the address of the PHY register to be read

Stop bit

Indicates the end of the transfer (always 0)

For a write register request, the length of the LREQ bit stream is 17 bits as shown in Table 18.

Table 18. Write Register Request

BIT(s)

NAME

DESCRIPTION

Start bit

Indicates the beginning of the transfer (always 1)

1−3

Request type

A 101 indicating this is a write register request.

4−7

Address

Identifies the address of the PHY register to be written to

8−15

Data

Gives the data that is to be written to the specified register address

Stop bit

Indicates the end of the transfer (always 0)

For an acceleration control request, the length of the LREQ data stream is 6 bits as shown in Table 19.

Table 19. Acceleration Control Request

BIT(s)

NAME

DESCRIPTION

Start bit

Indicates the beginning of the transfer (always 1)

1−3

Request type

A 110 indicating this is an acceleration control request.

Control

Asynchronous period arbitration acceleration is enabled if 1 and disabled if 0

Stop bIt

Indicates the end of the transfer (always 0)

For fair or priority access, the LLC sends the bus request (FairReq or PriReq) at least one clock after the

PHY-LLC interface becomes idle. If the CTL terminals are asserted to the receive state (10b) by the PHY, then

any pending fair or priority request is lost (cleared). Additionally, the PHY ignores any fair or priority requests

if the receive state is asserted while the LLC is sending the request. The LLC may then reissue the request one

clock after the next interface idle.

The cycle master node uses a priority bus request (PriReq) to send a cycle start message. After receiving or

transmitting a cycle start message, the LLC can issue an isochronous bus request (IsoReq). The PHY clears

an isochronous request only when the serial bus has been won.

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