AD7791

Data Sheet

Rev. A | Page 12 of 20

Bit Location

Bit Name

Description

MR5–MR4

0

This bit must be programmed with a Logic 0 for correct operation.

MR3

BO

Burnout Current Enable Bit. When this bit is set to 1 by the user, the 100 nA current sources in the signal

path are enabled. When BO = 0, the burnout currents are disabled. The burnout currents can be enabled

only when the buffer is active.

MR2

U/B

Unipolar/Bipolar Bit. Set by user to enable unipolar coding, i.e., zero differential input will result in

0x000000 output and a full-scale differential input will result in 0xFFFFFF output. Cleared by the user to

enable bipolar coding. Negative full-scale differential input will result in an output code of 0x000000,

zero differential input will result in an output code of 0x800000, and a positive full-scale differential input

will result in an output code of 0xFFFFFF.

MR1

BUF

Configures the ADC for buffered or unbuffered mode of operation. If cleared, the ADC operates in un-

buffered mode, lowering the power consumption of the device. If set, the ADC operates in buffered

mode, allowing the user to place source impedances on the front end without contributing gain errors

to the system.

MR0

0

This bit must be programmed with a Logic 0 for correct operation.

Table 10. Operating Modes

MD1

MD0

Mode

0

0

Continuous Conversion Mode (De-

fault)

0

1

Reserved

1

0

Single Conversion Mode

1

1

Power-Down Mode

FILTER REGISTER (RS1, RS0 = 1, 0; POWER-ON/RESET = 0x04)

The filter register is an 8-bit register from which data can be read or to which data can be written. This register is used to set the output

word rate. Table 11 outlines the bit designations for the filter register. FR0 through FR7 indicate the bit locations, FR denoting the bits are in

the filter register. FR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.

FR7

FR6

FR5

FR4

FR3

FR2

FR1

FR0

0(0)

0(0)

CDIV1(0)

CDIV0(0)

0(0)

FS2(1)

FS1(0)

FS0(0)

Table 11. Filter Register Bit Designations

Bit Location

Bit Name

Description

FR7–FR6

0

These bits must be programmed with a Logic 0 for correct operation.

FR5–FR4

CLKDIV1–

CDIV0

These bits are used to operate the AD7791 in the lower power modes. The clock is internally divided and

the power is reduced. In the low power modes, the update rates will scale with the clock frequency so

that dividing the clock by 2 causes the update rate to be reduced by a factor of 2 also.

00

Normal Mode

01

Clock Divided by 2

10

Clock Divided by 4

11

Clock Divided by 8

FR3

0

This bit must be programmed with a Logic 0 for correct operation.

FR2–FR0

FS2–FS0

These bits set the output word rate of the ADC. The update rate influences the 50 Hz/60 Hz rejection and

the noise. See Table 12, which shows the allowable update rates when normal power mode is used. In

the low power modes, the update rate is scaled with the clock frequency. For example, if the internal

clock is divided by a factor of 2, the corresponding update rates will be divided by 2 also.