Data Sheet

AD7687

Rev. E | Page 7 of 26

−40°C to +85°C, VDD = 2.3 V to 4.5 V, VIO = 2.3 V to 4.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.

See Figure 2 and Figure 3 for load conditions.

Table 5.

Parameter

Symbol

Min

Typ

Max

Unit

CONVERSION TIME: CNV RISING EDGE TO DATA AVAILABLE

0.7

3.2

µs

ACQUISITION TIME

1.8

µs

TIME BETWEEN CONVERSIONS

5

µs

CNV PULSE WIDTH (CS MODE)

10

ns

SCK PERIOD

CS Mode

25

ns

Chain Mode

VIO Above 3 V

29

ns

VIO Above 2.7 V

35

ns

VIO Above 2.3 V

40

ns

SCK TIME

Low

12

ns

High

12

ns

SCK FALLING EDGE

To Data Remains Valid

5

To Data Valid Delay

VIO Above 3 V

24

ns

VIO Above 2.7 V

30

ns

VIO Above 2.3 V

35

ns

CNV OR SDI

Low to SDO D15 MSB Valid (CS Mode)

VIO Above 2.7 V

18

ns

VIO Above 2.3 V

22

ns

High or Last SCK Falling Edge to SDO High Impedance (CS Mode)

25

ns

SDI

Valid Setup Time from CNV Rising Edge (CS Mode)

30

ns

Valid Hold Time from CNV Rising Edge (CS Mode)

0

ns

Valid Setup Time from SCK Falling Edge (Chain Mode)

5

ns

Valid Hold Time from SCK Falling Edge (Chain Mode)

4

ns

High to SDO High (Chain Mode with BUSY indicator)

36

ns

SCK

Valid Setup Time from CNV Rising Edge (Chain Mode)

5

ns

Valid Hold Time from CNV Rising Edge (Chain Mode)

8

ns

Timing Diagrams

500

µA

500

µA

1.4V

TO SDO

50pF

Figure 2. Load Circuit for Digital Interface Timing

30% VIO

70% VIO

Figure 3. Voltage Levels for Timing