AD7266 datasheet(21/29 Pages) AD

21 / 29 page

AD7266

Rev. B | Page 20 of 28

FULL POWER-DOWN MODE

This mode is intended for use in applications where throughput

rates slower than those in the partial power-down mode are

required, as power-up from a full power-down takes substan-

tially longer than that from partial power-down. This mode is

more suited to applications where a series of conversions

performed at a relatively high throughput rate are followed by a

long period of inactivity and thus power-down. When the

AD7266 is in full power-down, all analog circuitry is powered

down. Full power-down is entered in a similar way as partial

power-down, except the timing sequence shown in Figure 35

must be executed twice. The conversion process must be

interrupted in a similar fashion by bringing CS high anywhere

after the second falling edge of SCLK and before the 10th falling

edge of SCLK. The device enters partial power-down at this

point. To reach full power-down, the next conversion cycle

must be interrupted in the same way, as shown in

Once

Figure 37

CS is brought high in this window of SCLKs, the part

completely powers down.

Note that it is not necessary to complete the 14 SCLKs once CS

is brought high to enter a power-down mode.

To exit full power-down and power up the AD7266, a dummy

conversion is performed, as when powering up from partial

power-down. On the falling edge of CS, the device begins to

power up and continues to power up, as long as CS is held low

until after the falling edge of the 10th SCLK. The required

power-up time must elapse before a conversion can be initiated,

as shown in

. See the

section for the

power-up times associated with the AD7266.

Figure 38

Power-Up Times

SCLK

DOUTA

DOUTB

INVALID DATA

VALID DATA

110

THE PART BEGINS

TO POWER UP.

THE PART IS FULLY

POWERED UP; SEE

POWER-UP TIMES

SECTION.

tPOWER-UP1

Figure 36. Exiting Partial Power-Down Mode

THREE-STATE

110

SCLK

DOUTA

DOUTB

THREE-STATE

110

INVALID DATA

THE PART BEGINS

TO POWER UP.

THE PART ENTERS

PARTIAL POWER DOWN.

THE PART ENTERS

FULL POWER DOWN.

Figure 37. Entering Full Power-Down Mode

AD7266 датащи(PDF) 21 Page - Analog Devices

AD7266 датащи(HTML) 21 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

датащи скачать

ссылки URL