AD7265BCPZ datasheet(21/29 Pages) AD

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AD7265

Data Sheet

Rev. B | Page 20 of 28

To exit this mode of operation and power up the AD7265 again,

a dummy conversion is performed. On the falling edge of CS,

the device begins to power up and continues to power up as

long as CS is held low until after the falling edge of the 10th

SCLK. The device is fully powered up after approximately 1 μs

has elapsed, and valid data results from the next conversion, as

shown in Figure 36. If CS is brought high before the second

falling edge of SCLK, the AD7265 again goes into partial

power-down. This avoids accidental power-up due to glitches

on the CS line. Although the device may begin to power up on

the falling edge of CS, it powers down again on the rising edge

of CS. If the AD7265 is already in partial power-down mode

and CS is brought high between the second and 10th falling

edges of SCLK, the device enters full power-down mode.

FULL POWER-DOWN MODE

This mode is intended for use in applications where throughput

rates slower than those in the partial power-down mode are

required, as power-up from a full power-down takes

substantially longer than that from partial power-down. This

mode is more suited to applications where a series of

conversions performed at a relatively high throughput rate are

followed by a long period of inactivity and thus power-down.

When the AD7265 is in full power-down, all analog circuitry is

powered down. Full power-down is entered in a similar way as

partial power-down, except the timing sequence shown in

Figure 35 must be executed twice. The conversion process must

be interrupted in a similar fashion by bringing CS high anywhere

after the second falling edge of SCLK and before the 10th falling

edge of SCLK. The device enters partial power-down at this

point. To reach full power-down, the next conversion cycle

must be interrupted in the same way, as shown in Figure 37.

Once CS is brought high in this window of SCLKs, the part

completely powers down.

Note that it is not necessary to complete the 14 SCLKs once CS

is brought high to enter a power-down mode.

To exit full power-down and power up the AD7265, a dummy

conversion is performed, as when powering up from partial

power-down. On the falling edge of CS, the device begins to

power up and continues to power up, as long as CS is held low

until after the falling edge of the 10th SCLK. The required

power-up time must elapse before a conversion can be initiated,

as shown in Figure 38. See the Power-Up Times section for the

power-up times associated with the AD7265.

SCLK

DOUTA

DOUTB

INVALID DATA

VALID DATA

110

THE PART BEGINS

TO POWER UP.

THE PART IS FULLY

POWERED UP; SEE

POWER-UP TIMES

SECTION.

tPOWER-UP1

Figure 36. Exiting Partial Power-Down Mode

THREE-STATE

110

SCLK

DOUTA

DOUTB

THREE-STATE

110

INVALID DATA

THE PART BEGINS

TO POWER UP.

THE PART ENTERS

PARTIAL POWER DOWN.

THE PART ENTERS

FULL POWER DOWN.

Figure 37. Entering Full Power-Down Mode

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