AMERICAN MICROSYSTEMS, INC.

September 2000

9.18.00

2

FS6232-01

FS6232-01

FS6232-01

FS6232-01

Two-Way MP Motherboard Clock Generator IC

Two-Way MP Motherboard Clock Generator IC

Two-Way MP Motherboard Clock Generator IC

Two-Way MP Motherboard Clock Generator IC

ISO9001

ISO9001

ISO9001

ISO9001

Table 3: Pin Descriptions

Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI

DO = Digital Output; P = Power/Ground; # = Active-low pin

PIN

TYPE

NAME

DESCRIPTION

SUPPLY

CK48_0

One of two 3.3V 48MHz clock outputs, generated from the non-spread PLL

25

DIO

SEL_A

One of two latched inputs that select the HOST and MREF output frequency

VDD_48

CK48_1

One of two 3.3V 48MHz clock outputs, generated from the non-spread PLL

26

DIO

SEL_B

One of two latched inputs that select the HOST and MREF output frequency

VDD_48

35, 34, 31, 30

DO

CK66_0:3

Four 3.3V 66.67MHz clock outputs, generated from the spread spectrum PLL

VDD_66

50, 51

AO

HOST_P1

HOST_N1

Host clock pair #1; one of six pairs of current-steering differential current-mode outputs. The

current is established via a reference current at IREF and a multiplying factor set by ISEL_0:1

VDD_H

47, 48

AO

HOST_P2

HOST_N2

Host clock pair #2; one of six pairs of current-steering differential current-mode outputs

VDD_H

44, 45

AO

HOST_P3

HOST_N3

Host clock pair #3; one of six pairs of current-steering differential current-mode outputs

VDD_H

41, 42

AO

HOST_P4

HOST_N4

Host clock pair #4; one of six pairs of current-steering differential current-mode outputs

VDD_H

39

AI

IREF

A fixed precision resistor from this pin to ground provides a reference current used for the dif-

ferential current-mode HOST clock outputs

VDD

54

DO

MREF_N

One clock (180° out of phase with MREF_P) in a pair of outputs provided as a reference clock

to a memory clock driver

VDD_M

55

DO

MREF_P

One clock in a pair of outputs provided as a reference clock to a memory clock driver

VDD_M

8, 9, 11, 12,

14, 15, 17, 18,

20, 21

DO

PCI_0:9

Ten 3.3V 33.3MHz PCI clocks, lagging the CK66 clock by 1.5 to 3.5ns

VDD_P

28

DI

PWR_DWN#

Asynchronous active-low LVTTL power-down signal shuts down oscillator and PLL, puts all

clocks in low state. Complete clock cycles on all outputs will occur before shut down begins.

VDD_48

REF_0

One of two 3.3V buffered copies of the crystal reference frequency clock

2DIO

ISEL_0

One of two latched inputs that select the multiplying factor of the IREF reference current for the

HOST pair outputs

VDD_R

REF_1

One of two 3.3V buffered copies of the crystal reference frequency clock

3DIO

ISEL_1

One of two latched inputs that select the multiplying factor of the IREF reference current for the

HOST pair outputs

VDD_R

23

DI

SEL133/100# Selects 133MHz (logic high) or 100MHz (logic low) Host clock frequency

VDD_48

52

DI

SS_EN#

Active low spread-spectrum enable turns on spread spectrum modulation

VDD_M

38

P

VDD

3.3V core power supply

-

27

P

VDD_48

3.3V power supply for CK48 clock outputs

-

29, 36

P

VDD_66

3.3V power supply for CK66 clock outputs

-

43, 49

P

VDD_H

3.3V power supply for the differential HOST clock outputs

-

56

P

VDD_M

3.3V power supply for MREF clock outputs

-

10, 16, 22

P

VDD_P

3.3V power supply for PCI clock outputs

-

4

P

VDD_R

3.3V power supply for the REF clock output and the crystal oscillator

-

37

P

VSS

Core ground

-

24

P

VSS_48

Ground for the CK48 clock outputs

-

32, 33

P

VSS_66

Ground for the CK66 clock outputs

40, 46

P

VSS_H

Ground for the differential HOST clock outputs

-

53

P

VSS_M

Ground for the MREF clock outputs

-

7, 13, 19

P

VSS_P

Ground for the PCI clock outputs

-

1

P

VSS_R

Ground for the REF clock outputs and the crystal oscillator

-

5

AI

XIN

14.318MHz crystal oscillator input

VDD_R

6

AO

XOUT

14.318MHz crystal oscillator output

VDD_R