TLF5775

July 1986

DS8906 AMFM Digital Phase-Locked Loop Synthesizer

General Description

The DS8906 is a PLL synthesizer designed specifically for

use in AMFM radios It contains the reference oscillator a

dual modulus programmable divider and a 20-bit shift regis-

terlatch for serial data entry The device is designed to

operate with a serial data controller generating the neces-

sary division codes for each frequency and logic state infor-

mation for radio function inputsoutputs

The Colpitts reference oscillator for the PLL operates at 4

MHz A chain of dividers is used to generate a 500 kHz

clock signal for the external controller Additional dividers

generate a 125 kHz reference signal for FM and a 500 Hz

reference signal for AMSW One of these reference signals

is selected by the data from the controller for use by the

phase comparator Additional dividers are used to generate

a 50 Hz timing signal used by the controller for ‘‘time-of-

day’’

Data is transferred between the frequency synthesizer and

the controller via a 3 wire bus system This consists of a

data input line an enable line and a clock line When the

enable line is low data can be shifted from the controller

into the frequency synthesizer When the enable line is tran-

sitioned from low to high data entry is disabled and data

present in the shift register is latched

From the controller 22-bit data stream the first 2 bits ad-

dress the device permitting other devices to share the same

bus Of the remaining 20-bit data word the next 14-bits are

used for the PLL divide code The remaining 6 bits are con-

nected via latches to output pins These 6 bits can be used

to drive radio functions such as gain mute FM AM LW and

SW only These outputs are open collector Bit 18 is used

internally to select the AM or FM local oscillator input and to

select between the 500 Hz and 125 kHz reference A high

level at bit 18 indicates FM and a low level indicates AM

prescaler and a high speed charge pump The programma-

into the shift register (bits 1 – 14 after address) It is clocked

6364 prescaler from the FM input The AM input will work

at frequencies up to 8 MHz while the FM input works up to

120 MHz The AM band is tuned with a frequency resolution

of 500 Hz and the FM band is tuned with a resolution of 125

kHz The buffered AM and FM inputs are self-biased and

can be driven directly by the VCO thru a capacitor The ECL

phase comparator produces very accurate resolution of the

phase difference between the input signal and the reference

oscillator

The high speed charge pump consists of a switchable con-

charge pump will source current and sink current if the VCO

frequency is high

oscillator and reference chain to provide controller clocking

frequencies when the balance of the PLL is powered down

Features

Y

Uses inexpensive 4 MHz reference crystal

Y

thesis at FM frequencies

Y

FM resolution of 125 kHz allows usage of 107 MHz

ceramic filter distribution

Y

Serial data entry for simplified control

Y

50 Hz output for ‘‘time-of-day’’ reference with separate

Y

6-open collector buffered outputs for band switching

and other radio functions

Y

Separate AM and FM inputs AM input has 15 mV (typi-

cal) hysteresis

Connection Diagram

Dual-In-Line Package

TLF5775 – 1

Top View

Order Number DS8906N

See NS Package Number N20A

TRI-STATE

is a registered trademark of National Semiconductor Corp

C1995 National Semiconductor Corporation

RRD-B30M105Printed in U S A