DS3141 datasheet(2/88 Pages) DALLAS

2 / 88 page

DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers

2 of 88

TABLE OF CONTENTS

BLOCK DIAGRAM.......................................................................................................................... 6

APPLICATION EXAMPLE .............................................................................................................. 6

MAIN FEATURES ........................................................................................................................... 7

STANDARDS COMPLIANCE ......................................................................................................... 8

PIN DESCRIPTION ......................................................................................................................... 9

5.1

TRANSMIT FORMATTER LIU INTERFACE PINS ................................................................................. 9

5.2

RECEIVE FRAMER LIU INTERFACE PINS......................................................................................... 9

5.3

TRANSMIT FORMATTER SYSTEM INTERFACE PINS ........................................................................ 10

5.4

RECEIVE FRAMER SYSTEM INTERFACE PINS ................................................................................ 12

5.5

CPU BUS INTERFACE PINS ......................................................................................................... 14

5.6

JTAG INTERFACE PINS............................................................................................................... 14

5.7

SUPPLY, TEST, AND RESET PINS................................................................................................. 14

REGISTERS.................................................................................................................................. 15

6.1

STATUS REGISTER DESCRIPTION ................................................................................................ 17

FUNCTIONAL DESCRIPTION ...................................................................................................... 18

7.1

PIN INVERSIONS AND FORCE HIGH/LOW ...................................................................................... 18

7.2

TRANSMITTER LOGIC .................................................................................................................. 18

7.2.1

Transmit Clock ..................................................................................................................................... 18

7.2.2

Loss-of-Clock Detection....................................................................................................................... 19

7.3

RECEIVER LOGIC........................................................................................................................ 19

7.4

ERROR INSERTION...................................................................................................................... 20

7.5

LOOPBACKS ............................................................................................................................... 20

7.5.1

Line Loopback...................................................................................................................................... 20

7.5.2

Diagnostic Loopback............................................................................................................................ 20

7.5.3

Payload Loopback................................................................................................................................ 20

7.5.4

BERT and Loopback Interaction .......................................................................................................... 20

7.6

COMMON AND LINE INTERFACE REGISTERS ................................................................................. 22

7.6.1

Master Status Register (MSR) ............................................................................................................. 28

7.7

DS3/E3 FRAMER ....................................................................................................................... 32

7.7.1

DS3/E3 Framer Register Description................................................................................................... 32

7.8

DS3/E3 PERFORMANCE ERROR COUNTERS ................................................................................ 42

7.9

BERT........................................................................................................................................ 45

7.9.1

BERT Register Description .................................................................................................................. 45

7.10

HDLC CONTROLLER ............................................................................................................... 53

7.10.1

Receive Operation ............................................................................................................................... 53

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