TLF5862

June 1986

DP8481 TTL to 10k ECL Level Translator with Latch

General Description

This circuit translates TTL input levels to ECL output levels

and provides a fall-through latch The outputs are gated with

CS providing for wire ORing of outputs The strobe and chip

select inputs operate at ECL levels

Features

Y

16-pin flat-pack or DIP

Y

ECL control inputs

Y

CS provided for wire ORing of output bus

Y

10k ECL IO compatible

Y

30 ns typical propagation delay

Logic and Connection Diagram

Dual-In-Line Package

TLF5862 – 1

Top View

Truth Table

DQ

STR

CS

HL

L

H

LH

L

H

XQ

HH

XL

X

L

Order Number

DP8481F DP8481J or DP8481N

See NS Package

F16B J16A or N16A

C1995 National Semiconductor Corporation

RRD-B30M115Printed in U S A