CY2V995
Document #: 38-07435 Rev. *A
Page 3 of 10
In addition to the feedback dividers, the CY2V995 includes
output dividers on Bank3 and Bank4, which are controlled by
3F[1:0] and 4F[1:0] as indicated in Table 3 and 4, respectively.
The divider settings, output frequencies, and possible config-
urations of connecting FB to ANY output are summarized in
Table 5.
The 3-level FS control pin setting determines the nominal
operating frequency range of the divide-by-one outputs of the
device. The CY2V995 PLL operating frequency range that
corresponds to each FS level is given in Table 6.
The PE pin determines Whether the outputs synchronize to
the rising or the falling edge of the reference signal, as
indicated in Table 7.
The CY2V995 features split power supply buses for Banks 1
and 2, Bank 3 and Bank 4, which enables the user to obtain
both 3.3V and 2.5V output signals from one device. The core
power supply (VDD) must be set a level which is equal or higher
than that on any one of the output power supplies.
Governing Agencies
The following agencies provide specifications that apply to the
CY2V995. The agency name and relevant specification is
listed below.
Notes:
5.
LL disables outputs if TEST = MID and sOE# = HIGH.
6.
When 4Q[0:1] are set to run inverted (HH mode), sOE# disables these outputs HIGH when PE = HIGH or MID, sOE# disables them LOW when PE = LOW.
7.
These outputs are undivided copies of the VCO clock. Therefore, the formulas in this column can be used to calculate the VCO operating frequency (FNOM) at
a given reference frequency (FREF) and divider and feedback configuration. The user must select a configuration and a reference frequency that will generate
a VCO frequency that is within the range specified by FS pin. Please see Table 6.
8.
VDDQ1/3/4 must not be set at a level higher than that of VDD. They can be set at different levels from each other, e.g. VDD = 3.3V, VDDQ1 = 3.3V, VDDQ3 = 2.5V
and VDDQ4 = 2.5V.
Table 2. Power-down Mode
PD#
CY2V995
H
Enabled
L
Power Down
Table 3. Output Divider Settings – Bank 3
3F[1:0]
K – Bank3 Output Divider
LL[5]
2
HH
4
Other
1
Table 4. Output Divider Settings – Bank 4
4F[1:0]
M – Bank4 Output Divider
LL[5]
2
HH
Inverted[6]
Other
1
Table 5. Output Frequency Settings
Configuration
Output Frequency
FB Input
Connected to
1Q[0:1] and
2Q[0:1][7]
3Q[0:1]
4Q[0:1]
1Qn or 2Qn
N x FREF
N /x (1 / K) x
FREF
N x (1 / M) x
FREF
3Qn
N x K x FREF N x FREF
N x (K / M) x
FREF
4Qn
N x M x FREF N x (M / K) x
FREF
N x FREF
Table 6. Frequency Range Select
FS
PLL Frequency Range
L
24 to 50 MHz
M
48 to 100 MHz
H
96 to 200 MHz
Table 7. PE Settings
PE
Synchronization
L
Negative
H
Positive
Table 8. Power Supply Constraints
VDD
VDDQ1[8]
VDDQ3[8]
VDDQ4[8]
3.3V
3.3V or 2.5V
3.3V or 2.5V
3.3V or 2.5V
2.5V
2.5V
2.5V
2.5V
Agency Name
Specification
JEDEC
JESD 51 (Theta JA)
JESD 65 (Skew, Jitter)
IEEE
1596.3 (Jiter Specs)
UL-194_V0
94 (Moisture Grading)
MIL
883E Method 1012.1
(Therma Theta JC)
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