TLF10966

July 1996

CGS74B303 Octal Divide-by-2 Skew Clock Driver

General Description

These minimum skew clock drivers are designed for high

frequency Clock Generation and Support (CGS) applica-

tions These devices are ideal for duty cycle recovery appli-

cations with internal frequency divide-by-2 circuitry The de-

vices guarantee minimum skew across the outputs of a giv-

en device Skew parameters are also provided as a means

to measure duty cycle requirements as those found in high

speed clocking systems

Functional Description

The CGS74B303 contains eight flip-flops designed to have

low skew between outputs The eight outputs (six in-phase

with CLK and two out-of-phase) toggle on successive CLK

pulses PRE and CLR inputs are provided to set Q and Q

outputs high or low independent of CLK pin

Features

Y

Clock Generation and Support (CGS) Devices ideal for

high frequency signal generation or clock distribution

applications

Y

process

Y

1 ns pin-to-pin output skew

Y

Specification for transition skew to meet duty cycle

requirements

Y

Current sourcing 24 mA and current sinking of 48 mA

Y

Low dynamic power consumption above 20 MHz

Y

Guaranteed 4 kV ESD protection

Logic Diagram

Connection Diagram

TLF10966 – 3

Pin Assignment

SOlC (M)

TLF10966 – 1

Pin Description

Pin Names

Description

CLK

Clock Input

Outputs

PRE

Preset

CLR

Clear

Truth Table

Inputs

Outputs

CLR

PRE

CLK

LH

X

L

H

HL

X

H

L

LL

X

L

L

HH

u

Q

Q

HH

L

Q

Q

This state will not persist when CLR PRE returns to high

TRI-STATE

is a registered trademark of National Semiconductor Corporation

C1996 National Semiconductor Corporation

RRD-B30M86Printed in U S A

http

www nationalcom