AD7643BSTZ datasheet(7/29 Pages) AD

номер детали	AD7643BSTZ

подробное описание детали	18-Bit, 1.25 MSPS PulSAR ADC

PDF	29 Pages

Scroll/Zoom	100%

производитель	AD [Analog Devices]

домашняя страница	http://www.analog.com

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7 / 29 page

AD7643

Rev. 0 | Page 6 of 28

Table 4. Serial Clock Timings in Master Read After Convert Mode

DIVSCLK[1]

DIVSCLK[0]

Symbol

Unit

SYNC to SCLK First Edge Delay Minimum

t18

Internal SCLK Period Minimum

t19

Internal SCLK Period Maximum

t19

135

Internal SCLK High Minimum

t20

Internal SCLK Low Minimum

t21

SDOUT Valid Setup Time Minimum

t22

SDOUT Valid Hold Time Minimum

t23

0.5

SCLK Last Edge to SYNC Delay Minimum

t24

0.5

BUSY High Width Maximum

t28

0.84

1.14

1.72

2.88

μs

NOTE

IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND

SDOUT TIMING ARE DEFINED WITH A MAXIMUM LOAD

CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.

500µA

IOL

500µA

IOH

1.4V

TO OUTPUT

50pF

Figure 2. Load Circuit for Digital Interface Timing,

SDOUT, SYNC, and SCLK Outputs, CL = 10 pF

0.8V

tDELAY

Figure 3. Voltage Reference Levels for Timing

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