AD7329 datasheet(21/39 Pages) AD

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AD7329

Data Sheet

Rev. C | Page 20 of 38

TYPICAL CONNECTION DIAGRAM

Figure 34 shows a typical connection diagram for the AD7329.

In this configuration, the AGND pin is connected to the analog

ground plane of the system, and the DGND pin is connected to

the digital ground plane of the system. The analog inputs on the

AD7329 can be configured to operate in single-ended, true

differential, or pseudo differential mode. The AD7329 can operate

with either an internal or external reference. In Figure 34, the

AD7329 is configured to operate with the internal 2.5 V reference.

A 680 nF decoupling capacitor is required when operating with

the internal reference.

The VCC pin can be connected to either a 3 V or a 5 V supply

voltage. The VDD and VSS are the dual supplies for the high

voltage analog input structures. The voltage on these pins must

be equal to or greater than the highest analog input range

selected on the analog input channels (see Table 6 for more

information). The VDRIVE pin is connected to the supply voltage

of the microprocessor. The voltage applied to the VDRIVE input

controls the voltage of the serial interface.

AD7329

VCC

VDD1

SERIAL

INTERFACE

FILTERING/BUFFERING

µC/µP

VIN0

VIN1

VIN2

VIN3

VIN4

VIN5

VIN6

VIN7

REFIN/REFOUT

DOUT

VDRIVE

SCLK

DIN

DGND

10µF

0.1µF

MUXOUT+ ADCIN+

MUXOUT– ADCIN–

10µF

0.1µF

10µF

0.1µF

ANALOG INPUTS:

±10V, ±5V, ±2.5V,

0V TO +10V

+15V

–15V

680nF

VSS1

VCC +2.7V TO +5.25V

1MINIMUM VDD AND VSS SUPPLY VOLTAGES

DEPEND ON THE HIGHEST ANALOG INPUT

RANGE SELECTED.

AGND

10µF

0.1µF

+3V SUPPLY

Figure 34. Typical Connection Diagram, Single-Ended Mode

AD7329

VCC

VDD1

SERIAL

INTERFACE

FILTERING/BUFFERING

µC/µP

VIN0

VIN1

VIN2

VIN3

VIN4

VIN5

VIN6

VIN7

REFIN/REFOUT

DOUT

VDRIVE

SCLK

DIN

DGND

10µF

0.1µF

10µF

0.1µF

10µF

0.1µF

ANALOG INPUTS:

±10V, ±5V, ±2.5V,

0V TO +10V

+15V

–15V

680nF

VSS1

VCC +2.7V TO +5.25V

1MINIMUM VDD AND VSS SUPPLY VOLTAGES

DEPEND ON THE HIGHEST ANALOG INPUT

RANGE SELECTED.

AGND

10µF

0.1µF

+3V SUPPLY

Figure 35. Typical Connection Diagram, Differential Mode

ANALOG INPUT

Single-Ended Inputs

The AD7329 has a total of eight analog inputs when operating

in single-ended mode. Each analog input can be independently

programmed to one of the four analog input ranges. In applications

where the signal source is high impedance, it is recommended

to buffer the signal before applying it to the ADC analog inputs.

Figure 36 shows the configuration of the AD7329 in single-

ended mode.

AD73291

VIN+

V+

V–

VDD

VSS

VCC

AGND

1ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 36. Single-Ended Mode Typical Connection Diagram

True Differential Mode

The AD7329 can have four true differential analog input pairs.

Differential signals have some benefits over single-ended

signals, including better noise immunity based on the device’s

common-mode rejection and improvements in distortion

performance. Figure 37 defines the configuration of the true

differential analog inputs of the AD7329.

AD73291

VIN+

VIN–

1ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 37. True Differential Inputs

The amplitude of the differential signal is the difference

between the signals applied to the VIN+ and VIN− pins in

each differential pair (VIN+ − VIN−). VIN+ and VIN− should

be simultaneously driven by two signals of equal amplitude,

dependent on the input range selected, that are 180° out of

phase. Assuming the ±4 × VREF mode, the amplitude of the

differential signal is −20 V to +20 V p-p (2 × 4 × VREF),

regardless of the common mode.

The common mode is the average of the two signals

(VIN+ + VIN−)/2

and is therefore the voltage on which the two input signals are

centered.

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