AD7322 datasheet(29/37 Pages) AD

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AD7322

Data Sheet

Rev. B | Page 28 of 36

AUTOSHUTDOWN MODE (PM1 = 1, PM0 = 0)

Once the autoshutdown mode is selected, the AD7322 auto-

matically enters shutdown on the 15th SCLK rising edge. In

autoshutdown mode, all internal circuitry is powered down. The

AD7322 retains information in the registers during autoshutdown.

The track-and-hold is in hold mode during autoshutdown. On

the rising CS edge, the track-and-hold, which was in hold during

shutdown, returns to track as the AD7322 begins to power up.

The power-up from autoshutdown is 500 µs.

When the control register is programmed to transition to autoshut-

down mode, it does so on the 15th SCLK rising edge. Figure 47

shows the part entering autoshutdown mode. Once in autoshut-

down mode, the CS signal must remain low to keep the part in

autoshutdown mode. The AD7322 automatically begins to power

up on the CS rising edge. The tPOWER-UP for autoshutdown is

required before a valid conversion, initiated by bringing the

CS signal low, can take place. When this valid conversion is

complete, the AD7322 powers down again on the 15th SCLK

rising edge. The CS signal must remain low again to keep the part

in autoshutdown mode.

AUTOSTANDBY MODE (PM1 = 0, PM0 = 1)

In autostandby mode, portions of the AD7322 are powered

down, but the on-chip reference remains powered up. The

reference bit in the control register should be 1 to ensure that

the on-chip reference is enabled. This mode is similar to auto-

shutdown, but allows the AD7322 to power up much faster.

This allows faster throughput rates to be achieved.

As is the case with the autoshutdown mode, the AD7322 enters

standby on the 15th SCLK rising edge when the control register

is updated (see Figure 47). The part retains information in the

registers during standby. Once in autostandby mode, the CS

signal must remain low to keep the part in autostandby mode.

The AD7322 remains in standby until it receives a CS rising

edge. The ADC begins to power up on the CS rising edge. On

the CS rising edge, the track-and-hold, which was in hold mode

while the part was in standby, returns to track. The power-up

time from standby is 750 ns.

The user should ensure that 750 ns have elapsed before bringing

CS low to attempt a valid conversion. Once this valid conversion

is complete, the AD7322 again returns to standby on the 15th SCLK

rising edge. The CS signal must remain low to keep the part in

standby mode.

Figure 47 shows the part entering autoshutdown mode. The

sequence of events is the same when entering autostandby mode.

In Figure 47, the power management bits are configured for auto-

shutdown. For autostandby mode, the power management bits,

PM1 and PM0, should be set to 0 and 1, respectively.

SCLK

SDATA

DIN

VALID DATA

DATA INTO CONTROL REGISTER

tPOWER-UP

CONTROL REGISTER IS LOADED ON THE FIRST 15 CLOCKS,

PM1 = 1, PM0 = 0

PART ENTERS SHUTDOWN MODE

ON THE 15TH RISING SCLK EDGE

AS PM1 = 1, PM0 = 0

PART BEGINS TO POWER

UP ON CS RISING EDGE

THE PART IS FULLY POWERED UP

ONCE

tPOWER-UP HAS ELAPSED

Figure 47. Entering Autoshutdown/Autostandby Mode

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