Preliminary Technical Data

AD5040/AD5060

Rev. PrC | Page 13 of 17

Figure 22. AD5060 Input Register Contents

Figure 22. AD5040 Input Register Contents

SYNC Interrupt

For the AD5060, in normal write sequence, the SYNC line is

kept low for at least 24 falling edges of SCLK and the DAC is

updated on the 24th falling edge. However, if SYNC is brought

high before the 24th falling edge this acts as an interrupt to the

write sequence. The shift register is reset and the write

sequence is seen as invalid. Neither an update of the DAC

register contents or a change in the operating mode occurs—

clock edge.

Power-On-Reset

The AD5040/AD5060 contains a power-on-reset circuit that

controls the output voltage during power-up. The DAC register

is filled with zeros and the output voltage is zero volts/mid-

scale. It remains there until a valid write sequence is made to

the DAC. This is useful in applications where it is important to

know the state of the output of the DAC while it is in the

process of powering up.

Software Reset.

The AD5040/AD5060 can be put into software reset by setting

all in the Dac register to one. For the AD5060 this includes

writing ones to bits D23-D16, which in not the normal mode of

performed if a software reset command is started.

Power-Down Modes

The AD5040/AD5060 contains four separate modes of

operation. These modes are software-programmable by setting

two bits (PD1 and PD0) in the control register. Table I shows

how the state of the bits corresponds to the mode of operation

of the device.

Table I. Modes of Operation for the

AD5040/AD5060

PD1

PD0

Operating Mode

0

0

Normal Operation

Power-Down Mode

0

1

TRI-STATE

1

0

100 k

Ω to GND

1

1

1 k

Ω to GND *

*Not available for the AD5040; Reserved mode.

When both bits are set to 0, the part works normally with its

normal power consumption. However, for the three power-

down modes, the supply current falls to 200 nA at 5 V (50 nA at

3 V). Not only does the supply current fall but the

output stage is also internally switched from the output of

the amplifier to a resistor network of known values. This

has the advantage that the output impedance of the part

is known while the part is in power-down mode.

There are three different options. The output is

connected internally toGNDthrougha1k

Ω resistor,a100 kΩ resistor

orit is leftopen-circuited(Three-State).Theoutput stageis illustrated in

Figure24.

Figure 24. Output Stage During Power-Down