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MM54HC107 датащи(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
номер детали MM54HC107
подробное описание детали  MM54HC107/MM74HC107 Dual J-K Flip-Flops with Clear
PDF  6 Pages
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производитель  NSC [National Semiconductor (TI)]
домашняя страница  http://www.national.com
Logo NSC - National Semiconductor (TI)

MM54HC107 датащи(HTML) 3 Page - National Semiconductor (TI)

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AC Electrical Characteristics VCCe5V TAe25 C CLe15 pF tretfe6ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Units
Limit
fMAX
Maximum Operating
50
30
MHz
Frequency
tPHL tPLH
Maximum Propagation
16
21
ns
Delay Clock to Q or Q
tPHL tPLH
Maximum Propagation
21
26
ns
Delay Clear to Q or Q
tREM
Minimum Removal Time
10
20
ns
Clear to Clock
ts
Minimum Setup Time
14
20
ns
J or K to Clock
tH
Minimum Hold Time
b
30
ns
J or K from Clock
tW
Minimum Pulse Width
10
16
ns
Clock or Clear
AC Electrical Characteristics CLe50 pF tretfe6 ns (unless otherwise specified)
TAe25 C
74HC
54HC
Symbol
Parameter
Conditions
VCC
TAeb40 to 85 CTAeb55 to 125 C
Units
Typ
Guaranteed Limits
fMAX
Maximum Operating
20V
9
5
4
3
MHz
Frequency
45V
45
27
21
18
MHz
60V
53
31
24
20
MHz
tPHL tPLH
Maximum Propagation
20V
70
126
160
185
ns
Delay Clock to Q or Q
45V
18
25
32
37
ns
60V
16
21
27
32
ns
tPHL tPLH
Maximum Propagation
20V
126
155
194
250
ns
Delay Clear to Q or Q
45V
25
31
39
47
ns
60V
21
26
32
40
ns
tREM
Minimum Removal Time
20V
55
100
125
150
ns
Clear to Clock
45V
11
20
25
30
ns
60V
9
17
21
25
ns
ts
Minimum Setup Time
20V
77
100
125
150
ns
J or K to Clock
45V
15
20
25
30
ns
60V
13
17
21
25
ns
tH
Minimum Hold Time
20V
b
30
0
0
ns
J or K to Clock
45V
b
30
0
0
ns
60V
b
30
0
0
ns
tW
Minimum Pulse Width
20V
55
80
100
120
ns
Clear or Clock
45V
11
16
20
24
ns
60V
10
14
18
21
ns
tTLH tTHL
Maximum Output Rise
20V
30
75
95
110
ns
and Fall Time
45V
8
15
19
22
ns
60V
7
13
16
19
ns
tr tf
Maximum Input Rise and
20V
1000
1000
1000
ns
Fall Time
45V
500
500
500
ns
60V
400
400
400
ns
CPD
Power Dissipation
(per flip-flop)
80
pF
Capacitance (Note 5)
CIN
Maximum Input
5
10
10
10
pF
Capacitance
Note 5
CPD determines the no load dynamic power consumption PDeCPD VCC2 faICC VCC and the no load dynamic current consumption ISeCPD VCC faICC
3



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