PI6CU877NF datasheet(5/11 Pages) PERICOM

5 / 11 page

PS8689B

08/05/04

PI6CU877

PLL Clock Driver for

1.8V DDR2 Memory

Timing Requirements (Over recommended operating free-air temperature)

Symbol

Decription

AVDD, VDDQ = 1.8V ±0.1V

Units

Min.

Max.

FCK

Operation clock frequency(7, 8)

300

MHz

Application clock frequency(7, 9)

160

270

tDC

Input clock duty cycle

Stabalization time(10)

µs

tOFF

Device power down(10)

Notes:

The PLL is able to handle spread spectrum induced skew.

Operating clock frequency indicates a range over which the PLL is able to lock, but in which it is not required to meet the other

timing parameters. (Used for low-speed debug).

Application clock frequency indicates a range over which the PLL must meet all timing parameters.

10. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference

signal after power up . During normal operation, the stabilization time is also the time required for the integrated PLL circuit to

obtain phase lock of its feedback signal to its reference signal when CK and CK go to a logic low state, enter the power-down

mode and later return to active operation. CK and CK maybe left floating after they have been driven low for one complete clock cycle.

DC Specifications

Param-

eter

Description

Test Condition

AVDD,

VDDQ

Min.

Typ.

Max.

Units

VIK

All Inputs

II= -18mA

1.7V

1.2

VOH

HIGH output voltage

IOH = -100µA

1.7 to

1.9V

VDDQ

-0.2

IOH = -9mA

1.7

1.1

IODL

Output disabled low current

OE = L, VODL = 100mV

1.7V

100

µA

VOD

Output differenital voltage, the magniture of the difference

between the true and complimentary outputs, see fig. 9 for

dimentions

0.6

CK, CK

VI = VDDQ or GND

1.9V

±250

µA

OE, OS, FBIN, FBIN

VI = VDDQ or GND

±10

IDDLD

Static Supple current, IDDQ + IADD CK and CK = L

500

IDD

Dynamic supply current, IDDQ +

IADD, see note 6 for CPD calcula-

tion

CK and CK = 270MHz,

all outputs are open (not

connected to a PCB)

300

CK, CK

VI = VDDQ or GND

1.8V

FBIN, FBIN

VI = VDDQ or GND

CI(∆)

CK, CK

VI = VDDQ or GND

0.25

FBIN, FBIN

VI = VDDQ or GND

0.25

Notes:

Total IDD = IDDQ + IADD = FCK *CPD *VDDQ, solving for CPD = (IDDQ + IADD)/(FCK*VDDQ) where FCK is the input frequency, VDDQ is the

power supply and CPD is the Power Dissipation Capacitance.

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