6

PS8689B

08/05/04

PI6CU877

PLL Clock Driver for

1.8V DDR2 Memory

AC Specifications

Parameter

Description

Diagram

Units

Min.

Nom.

Max.

ten

OE to and Y/Y

see Fig 11

8

ns

tdis

OE to and Y/Y

see Fig 11

8

tjit(cc+)

Cycle-to-cycle jitter

see Fig 4

0

40

ps

tjit(cc-)

0

-40

t(Ø)

see Fig 5

-50

50

t(Ø)dyn

Dynamic phase offset

see Fig 10

-50

50

tsk(o)

Output clock skew

see Fig 6

40

tjit(per)

see Fig 7

-40

40

tjit(hper)

see Fig 8

-75

75

slr(i)

Input clock slew rate

see Fig 9

1

2.5

4

V/ns

Output enable (OE)

see Fig 9

0.5

slr(o)

see Fig 1, 9

1.5

2.5

3

see Fig 2

-0.1

+0.1

V

The PLL on the PI6CU877 is capable of meeting all the above test parameters while supporting SSC synthesirers

with the following parameters:

SSC modulation frequency

30.00

33

kHz

SSC clock input frequency deviation

0.00

-0.50

%

PI6CU877 PLL design should target the values below to minimize the SCC induced skew:

PLL Loop Bandwidth

2.0

MHz

Notes:

11. Static Phase Offset does not include Jitter

12. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each other.

13. VOX specified at the DRAM clock input or the test load.

14. To eliminate the impact of input slew rates on static phase offset, the input slew rates of Reference Clock Input CK, CK and Feedback Clock

Input FBIN, FBIN are recommended to be nearly equal. The 2.5V/ns slew rates are shown as a recommended target. Compliance with these

Nom values is not mandatory if it can be adequately demonstrated that alternative characteristics meet the requirements of the registered

DDR2 DIMM application.

15. There are two terminations that are used with the above ac tests. The load/board in Figure 2 is used to measure the input and output differen-

tial-pair cross-voltage only. The load/board in Figure 3 is used to measure all other tests. For consistency, equal length cables should be used.

16. The Output slew rate is determined from IBIS model load shown in Figure1. It is measured single-ended.