TPS2392

TPS2393

SLUS536C − AUGUST 2002 − REVISED AUGUST 2004

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21

APPLICATION INFORMATION

setting the fault timing capacitor

timeout period permits riding out spurious current glitches and surges that may occur during operation of the

system, and prevents indefinite sourcing into faulted loads swapped into a live system. However, to ensure

smooth voltage ramping under all conditions of load capacitance and input supply potential, the minimum

timeout should be set to accommodate these system variables. To do this, a rough estimate of the maximum

voltage ramp time for a completely discharged plug-in card provides a good basis for setting the minimum timer

delay.

Due to the three-phase nature of the load current at turn-on, the load voltage ramp has potentially three distinct

phases and is seen by comparing Figure 1 and Figure 2. This profile depends on the relative values of load

capacitance, input dc potential, maximum current limit and other factors. The first two phases are characterized

by the two different slopes of the current ramp; the third phase, if required to complete load charging, is the

constant-current charging at IMAX. Considering the two current ramp phases to be one period at an average

di/dt simplifies calculation of the required timing capacitor.

t

C

IRAMP

where:

During this current ramp period, the load voltage magnitude which is attained is estimated by equation (4).

V

i

AVG

2

C

L

C

IRAMP

100

R

SENSE

t

SS

2

where:

turn-on, considering the typical output values.

If the result of equation (4) is larger than the maximum input supply value, then the load can be expected to

charge completely during the inrush slewing portion of the insertion event. However, if this voltage is less than

remaining amount of time required at IMAX is determined from equation (5).

t

C

L

V

V

REF_K(min)

R

SENSE

where:

(3)

(4)

(5)