AD9957SLASHPCBZ datasheet(50/62 Pages) AD

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Data Sheet

AD9957

Rev. E | Page 49 of 61

I/O_UPDATE, SYNC_CLK, AND SYSTEM CLOCK

RELATIONSHIPS

The I/O_UPDATE pin is used to transfer data from the serial

I/O buffer to the active registers in the device. Data in the buffer

is inactive.

SYNC_CLK is a rising edge active signal. It is derived from the

system clock and a divide-by-4 frequency divider. SYNC_CLK,

which is externally provided, can be used to synchronize

external hardware to the AD9957 internal clocks.

I/O_UPDATE initiates the start of a buffer transfer. It can

be sent synchronously or asynchronously relative to the

SYNC_CLK. If the setup time between these signals is met,

then constant latency (pipeline) to the DAC output exists.

For example, if repetitive changes to phase offset via the SPI

port is desired, the latency of those changes to the DAC output

is constant; otherwise, a time uncertainty of one SYNC_CLK

period is present.

By default, the I/O_UPDATE pin is an input that serves as a

strobe signal to allow synchronous update of the device oper-

ating parameters. A rising edge on I/O_UPDATE initiates

transfer of the register contents to the internal workings of

the device. Alternatively, the transfer of programmed data from

the programming registers to the internal hardware can be

accomplished by changing the state of the PROFILE[2:0] pins.

The timing diagram shown in Figure 64 depicts when the data

in the buffer is transferred to the active registers.

SYNC_CLK

SYSCLK

NN + 1

N – 1

DATA IN

REGISTERS

DATA IN

I/O BUFFERS

N + 1

N + 2

I/O_UPDATE

THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM THE ASYNCHRONOUSLY LOADED I/O BUFFERS AT POINT B.

Figure 64. I/O_UPDATE Transferring Data from I/O Buffer to Active Registers

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