AD9857AST datasheet(11/41 Pages) AD

11 / 41 page

AD9857

Rev. C | Page 10 of 40

Pin Number

Mnemonic

I/O

Function

35, 37, 38, 43,

48, 54, 58, 64

AVDD

3.3 V Analog Power pin(s).

36, 39, 40, 42,

44, 47, 53, 56,

59, 61, 65

AGND

Analog Ground pin(s).

IOUT

DAC Output pin. Normal DAC output current (analog).

IOUT

DAC Complementary Output pin. Complementary DAC output current (analog).

DAC_BP

DAC Reference Bypass. Typically not used.

DAC_RSET

DAC Current Set pin. Sets DAC reference current.

PLL_FILTER

PLL Filter. R-C network for PLL filter.

DIFFCLKEN

Clock Mode Select pin. A logic high on this pin selects DIFFERENTIAL REFCLK input mode. A logic

low selects the SINGLE-ENDED REFCLK input mode.

REFCLK

Reference Clock pin. In single-ended clock mode, this pin is the Reference Clock input. In differential

clock mode, this pin is the positive clock input.

REFCLK

Inverted Reference Clock pin. In differential clock mode, this pin is the negative clock input.

DPD

Digital Power-Down pin. Assertion of this pin shuts down the digital sections of the device to

conserve power. However, if selected, the PLL remains operational.

RESET

Hardware RESET pin. An active high input that forces the device into a predefined state.

PLL_LOCK

PLL Lock pin. Active high output signifying, in real time, when PLL is in lock state.

CIC_OVRFL

CIC Overflow pin. Activity on this pin indicates that the CIC Filters are in “overflow” state. This pin is

typically low unless a CIC overflow occurs.

PDCLK/FUD

I/O

Parallel Data Clock/Frequency Update pin. When not in single-tone mode, this pin is an output

signal that should be used as a clock to synchronize the acceptance of the 14-bit parallel

data-words on Pins D13–D0. In single-tone mode, this pin is an input signal that synchronizes the

transfer of a changed frequency tuning word (FTW) in the active profile (PSx) to the accumulator

(FUD = frequency update signal). When profiles are changed by means of the PS–PS1 pins, the FUD

does not have to be asserted to make the FTW active.

TxENABLE

When TxENABLE is asserted, the device processes the data through the I and Q data pathways;

otherwise 0s are internally substituted for the I and Q data entering the signal path. The first data

word accepted when the TxENABLE is asserted high is treated as I data, the next data word is Q data,

and so forth.

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