AD650

Data Sheet

Rev. E | Page 18 of 20

In signal recovery applications of a PLL, the desired output

signal is the voltage applied to the oscillator. In these situations,

a linear relationship between the input frequency and the

output voltage is desired; the AD650 makes a superb oscillator

for FM demodulation. The wide dynamic range and

outstanding linearity of the AD650 VFC allow simple

embodiment of high performance analog signal isolation or

telemetry systems. The circuit shown in Figure 22 uses a digital

phase detector that also provides proper feedback in the event

of unequal frequencies. Such phase-frequency detectors (PFDs)

are available in integrated form. For a full discussion of phase-

F.M. Gardner, (John Wiley & Sons, Inc., 1979).

An analysis of this circuit must begin at the 7474 Dual D flip

flop. When the input carrier matches the output carrier in both

phase and frequency, the Q outputs of the flip flops rise at

exactly the same time. With two zeros, and then two ones on

the inputs of the exclusive or (XOR) gate, the output remains

low keeping the DMOS FET switched off. Also, the NAND gate

goes low resetting the flip-flops to zero. Throughout this entire

cycle, the DMOS integrator gate remains off, allowing the

voltage at the integrator output to remain unchanged from the

previous cycle. However, if the input carrier leads the output

carrier by a few degrees, the XOR gate is turned on for the short

low during the mismatch time, a negative current is fed into the

integrator, causing its output voltage to rise. This in turn

increases the frequency of the AD650 slightly, driving the

system towards synchronization. In a similar manner, if the

input carrier lags the output carrier, the integrator is forced

down slightly to synchronize the two signals.

Using a mathematical approach, the ±25 μA pulses from the

radian

/

amperes

10

4

2

μA

25

6

−

×

=

π

=

d

K

(9)

Also, the V/F converter is configured to produce 1 MHz in

response to a 10 V input so its gain (Ko) is

sec

volt

radians

10

3

.

6

V

10

Hz

10

1

2

5

6

×

×

=

×

×

π

=

O

K

(10)

The dynamics of the phase relationship between the input and

output signals can be characterized as a second order system

C

K

K

d

o

ω

(11)

and damping factor (ζ) is

2

d

CK

R

=

ζ

(12)

For the values shown in Figure 22, these relations simplify to a

natural frequency of 35 kHz with a damping factor of 0.8.

For a simple approach to determine component values for other

PLL frequencies and VFC full-scale voltage, follow these steps:

MAX

MAX

o

V

F

K

×

π

= 2

(13)

2. Calculate a value for C based upon the desired loop

narrow even though it is transmitted over a 1 MHz carrier.

sec

Rad

10

1

7

2

×

×

×

×

=

−

F

V

f

K

C

n

o

(14)

where:

C units = farads

3. Calculate R to yield a damping factor of approximately 0.8

using this equation:

V

K

f

R

o

n

Ω

×

×

×

=

Rad

10

5

.

2

6

(15)

where:

R units = ohms

If in actual operation the PLL overshoots or hunts excessively

before reaching a final value, the damping factor can be raised

by increasing the value of R. Conversely, if the PLL is

overdamped, a smaller value of R should be used.