LC450029PKB

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10

(2) When CL is stopped at the high level

Note: DD is the direction data.

• CCB address .......... “41H”

• D1 to D208 ............ Display data

• EXF ....................... Ratio of dividing frequency in external clock operating mode setting control data

• DT ......................... 1/4-duty drive or 1/3-duty drive switching control data

• DN ......................... The number of the maximum display segments setting control data

• FC0 to FC2 ............ Common/segment output waveform frame frequency control data

• OC ......................... Internal oscillator operating mode/external clock operating mode switching control data

• SC .......................... Segment on/off (off waveform output) control data

• BU ......................... Normal mode/power-saving mode control data

FC0

SC

B1

B0

D2

D1

0

0

0

0

1

D53

D48

D47

DI

CL

CE

B3

B2

A1

A0

A3

A2

1

0

0

D50

D49

D52

D51

0

D54

0

0

0

EXF

0

DT

0

DN

BU

0

0

0

OC

FC1 FC2

0

B1

B0

0

0

0

0

1

D107

D102

D56

D55

B3

B2

A1

A0

A3

A2

1

0

0

0

D108

0

0

0

1

0

D106

D105

D104

D103

0

0

0

0

0

0

0

0

0

0

0

D101

0

B1

B0

0

0

0

0

1

0

D156

D110

D109

D155

B3

B2

A1

A0

A3

A2

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

D157 D158 D159 0

Fixed data

16 bits

DD

2 bits

Control data

16 bits

Display data

54 bits

CCB address

8 bits

DD

2 bits

Display data

54 bits

CCB address

8 bits

Fixed data

19 bits

DD

2 bits

Display data

51 bits

CCB address

8 bits