AD9864 datasheet(31/48 Pages) AD

31 / 48 page

AD9864

Data Sheet

Rev. A | Page 30 of 47

Figure 50 shows the nominal signal transfer function

magnitude for frequencies near the fCLK/8 pass band. The width

of the pass band determines the transfer function droop, but

even at the lowest oversampling ratio (48) where the pass band

edges are at ±fCLK/192 (±0.005 fCLK), the gain variation is less

than 0.5 dB. Also consider the amount of attenuation offered by

the signal transfer function near fCLK/8 when determining the

narrow-band IF filtering requirements preceding the AD9864.

–0.10

–5

–10

NORMALIZED FREQUENCY (RELATIVE TO

fCLK)

–15

–20

–0.05

0.05

0.10

Figure 50. Magnitude of the Signal Transfer Function of the ADC near fCLK/8

Tuning of the Σ-∆ modulator’s two continuous-time resonators

is essential in realizing the full dynamic range of the ADC, and

must be performed upon system startup. To facilitate tuning of

the LC tank, a capacitor array is internally connected to the MXOP

and MXON pins. The capacitance of this array is programmable

from 0 pF to 200 pF ± 20% and can be programmed either

automatically or manually via the SPI port. The capacitors of

the active RC resonator are similarly programmable. Note that

the AD9864 can be placed in and out of its standby mode without

retuning since the tuning codes are stored in the SPI registers.

When tuning the LC tank, the sampling clock frequency must

be stable and the LNA/mixer, LO synthesizer, and ADC must all

be placed in standby. Because large LO and IF signals

(>−40 dBm) present at the inputs of the AD9864 can corrupt

the calibration, these signals must be minimized or disabled

during the calibration sequence. Tuning is triggered when the

ADC is taken out of standby if the TUNE_LC bit of Register

0x1C has been set. This bit clears when the tuning operation is

complete (less than 6 ms). The tuning codes can be read from

the 3-bit CAPL1 (0x1D) and the 6-bit CAPL0 (0x1E) registers.

In a similar manner, tuning of the RC resonator is activated if

the TUNE_RC bit of Register 0x1C is set when the ADC is

taken out of standby. This bit clears when tuning is complete.

The tuning code can be read from the CAPR (0x1F) register.

Setting both the TUNE_LC and TUNE_RC bits tunes the LC

tank and the active RC resonator in succession. During tuning,

the ADC is not operational and neither data nor a clock is

available from the SSI port.

The following mechanisms prevent the tuning procedure from

finishing (that is, Register 0x1C does not clear):

•

CLK signal is not present or scaled/biased properly into

CLKP (and/or CLKN) pin such that internal clock receiver

does not square-up the input clock signal. To determine if

the CLK input signal is being received correctly, a clock

signal appears at the CLKOUT when the ADC is not in

standby mode (Register 0x00), and the CLKOUT buffer is

not three-stated (Register 0x18).

•

LC resonator fails to resonate during tune operation.

Check to see proper values are used for LC tank and that it

is connected to MXOP/MXON pins. Also check if 100 pF

capacitors are connected between MXOP (MXON) and

IF2P (IF2N) pins.

•

SYCNB pin is low.

•

Capacitor value (between the MXOP/MXON and

IF2P/IF2N pins) is larger than 100 pF.

Table 20 lists the recommended sequence of the SPI commands for

tuning the ADC, and Table 21 lists all of the SPI registers associated

with band-pass Σ-∆ ADC. Note that the recommended sequence

includes additional steps for robustness. These steps are additional

measures to prevent the back-end ADC from generating an

internal unstable signal that locks the state machine, thus

preventing resonator tuning. It also allows five attempts to calibrate

the resonators. As a further safeguard, the user can save the settings

for Register 0x1D, Register 0x1E, and Register 0x1F determined

during factory test and reload these settings after five attempts.

Note that that the occurrence of this tuning issue is extremely

rare among devices shipped to date, and the occurrence among

any suspect devices being quite low (<0.1%).

Table 20. Tuning Sequence

Address

(Hex)

Value

(Hex)

Comments

0x3E

0x47

Disable internal ADC unstable signal.

Enable RC Q enhancement.

Bypass RC and SC resonators.

0x38

0x01

Enable manual control of feedback DAC

0x39

0x0F

Set DAC to midscale

0x00

0x45

LO synthesizer, LNA/mixer, and ADC are

placed in standby.1

0x1C

0x03

Set TUNE_LC and TUNE_RC. Wait for CLK to

stabilize if CLK synthesizer used.

0x00

0x44

Take the ADC out of standby. Wait for 0x1C

to clear (<6 ms).

0x1C

0x00

If 0x1C does not clear, clear 0x1C and make

five attempts before exiting loop.

0x38

0x00

Disable manual control of feedback DAC

0x3E

0x00

Re-enable ADC unstable signal.

Disable RC Q enhancement.

Disable bypass of RC and SC resonators.

0x00

0x40

LNA/mixer (and LO SYN if used) can now be

taken out of standby

If external CLK VCO or source is used, the CLK oscillator must also be

disabled. Large IF or LO signals can corrupt the calibration; these signals

must be disabled during the calibration sequence.

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